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K24C020-DCTG-A PDF预览

K24C020-DCTG-A

更新时间: 2024-10-28 03:27:15
品牌 Logo 应用领域
伊泰克 - ESTEK 光电二极管
页数 文件大小 规格书
13页 1114K
描述
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages

K24C020-DCTG-A 数据手册

 浏览型号K24C020-DCTG-A的Datasheet PDF文件第1页浏览型号K24C020-DCTG-A的Datasheet PDF文件第2页浏览型号K24C020-DCTG-A的Datasheet PDF文件第3页浏览型号K24C020-DCTG-A的Datasheet PDF文件第5页浏览型号K24C020-DCTG-A的Datasheet PDF文件第6页浏览型号K24C020-DCTG-A的Datasheet PDF文件第7页 
24C02 / 24C04 / 24C08 / 24C16  
Device Operation  
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA  
pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods  
will indicate a start or stop condition as defined below.  
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other  
command (see to Figure 2 on page 4).  
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop  
command will place the EEPROM in a standby power mode (see Figure 2 on page 4).  
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The  
EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.  
STANDBY MODE: The 24C02/ 24C04/ 24C08/ 24C16 features a low-power standby mode which is enabled: (a)  
upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations  
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by  
following these steps:  
1. Clock up to 9 cycles.  
2. Look for SDA high in each cycle while SCL is high.  
3. Create a start condition.  
Figure 1: Data Validity  
SDA  
SCL  
DATA STABLE  
DATA STABLE  
DATA  
CHANGE  
Figure 2: Start and Stop Definition  
SDA  
SCL  
START  
STOP  
BEIJING ESTEK ELECTRONICS CO.,LTD  
4

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