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JANSD2N7381 PDF预览

JANSD2N7381

更新时间: 2024-02-24 10:27:08
品牌 Logo 应用领域
美高森美 - MICROSEMI 局域网晶体管
页数 文件大小 规格书
7页 646K
描述
Power Field-Effect Transistor, 9.4A I(D), 200V, 0.49ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN

JANSD2N7381 技术参数

生命周期:End Of Life零件包装代码:TO-257AA
包装说明:FLANGE MOUNT, R-XSFM-P3针数:3
Reach Compliance Code:compliantECCN代码:EAR99
风险等级:5.64配置:SINGLE
最小漏源击穿电压:200 V最大漏极电流 (ID):9.4 A
最大漏源导通电阻:0.49 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:TO-257AAJESD-30 代码:R-XSFM-P3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:FLANGE MOUNT
极性/信道类型:N-CHANNEL认证状态:Qualified
参考标准:MIL-19500/614表面贴装:NO
端子形式:PIN/PEG端子位置:SINGLE
晶体管元件材料:SILICONBase Number Matches:1

JANSD2N7381 数据手册

 浏览型号JANSD2N7381的Datasheet PDF文件第2页浏览型号JANSD2N7381的Datasheet PDF文件第3页浏览型号JANSD2N7381的Datasheet PDF文件第4页浏览型号JANSD2N7381的Datasheet PDF文件第5页浏览型号JANSD2N7381的Datasheet PDF文件第6页浏览型号JANSD2N7381的Datasheet PDF文件第7页 
JANSR2N7381  
Qualified Levels:  
JANSD, JANSR and  
JANSF  
Radiation Hardened N-Channel MOSFET  
Qualified per MIL-PRF-19500/614  
QPL RANGE and RAD LEVEL  
Radiation  
Level  
JANSD2N7381  
JANSR2N7381  
JANSF2N7381  
TID  
10 Krad  
100 Krad  
300 Krad  
DESCRIPTION  
These products are well suited for Space level applications requiring Total Dose radiation  
(TID) tolerance and Single Event capability. This 2N7381 is available in three qualified  
radiation levels and is packaged in a hermetic TO-257 outline. These products have all the  
same performance features of industry standard MOSFETs and may be used for most voltage  
control and fast switching applications.  
TO-257AA  
Package  
Important: For the latest information, visit our website http://www.microsemi.com.  
FEATURES  
Ease of paralleling  
Hermetically sealed package  
Low gate charge  
Single event hardened for space applications  
RHA level JANS qualifications available per MIL-PRF-19500/614.  
(See part nomenclature for all available options.)  
APPLICATIONS / BENEFITS  
Space level DC-DC converters  
Satellite Motor Control circuits  
Synchronous rectification  
Linear-mode applications  
MAXIMUM RATINGS @ TC = +25 ºC unless otherwise stated  
Parameters / Test Conditions  
Operating & Storage Junction Temperature Range  
Thermal Resistance Junction-to-Case (see Figure 4)  
Symbol  
TJ & Tstg  
RӨJC  
Value  
-55 to +150  
1.67  
Unit  
°C  
oC/W  
Total Power Dissipation  
@ TA = +25 °C  
2
75  
PT  
W
@ TC = +25 °C (1)  
MSC – Lawrence  
6 Lake Street,  
Lawrence, MA 01841  
Tel: 1-800-446-1158 or  
(978) 620-2600  
Gate-Source Voltage, dc  
VGS  
ID1  
ID2  
IDM  
IS  
± 20  
V
A
A
A
A
Drain Current, dc @ TC = +25 ºC (2) (3)  
Drain Current, dc @ TC = +100 ºC (2) (3)  
Off-State Current (Peak Total Value) (4)  
Source Current  
9.4  
6.0  
37.6  
9.4  
Fax: (978) 689-0803  
NOTES: 1. Derated linearly 0.6 W/ºC for TC > +25 ºC  
MSC – Ireland  
2. The following formula derives the maximum theoretical ID limit. ID is limited by package and internal  
wires and may also be limited by pin diameter:  
Gort Road Business Park,  
Ennis, Co. Clare, Ireland  
Tel: +353 (0) 65 6840044  
Fax: +353 (0) 65 6822298  
3. See Figure 3 for maximum drain current graphs  
4. IDM = 4 X ID1 as calculated in note (2)  
Website:  
www.microsemi.com  
T4-LDS-0124, Rev. 3 (11/18/13)  
©2013 Microsemi Corporation  
Page 1 of 7  

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