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JANSD2N7382

更新时间： 2023-05-15 00:00:00
品牌 Logo 应用领域
美高森美 - MICROSEMI 局域网晶体管
页数 文件大小 规格书
4页 214K
描述
Power Field-Effect Transistor, 11A I(D), 100V, 0.35ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-257AA, TO-257AA, 3 PIN

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JANSD2N7382 技术参数

生命周期：Obsolete零件包装代码：TO-257AA
包装说明：FLANGE MOUNT, R-XSFM-P3针数：3
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：5.67外壳连接：ISOLATED
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：100 V
最大漏极电流 (ID)：11 A最大漏源导通电阻：0.35 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJEDEC-95代码：TO-257AA
JESD-30 代码：R-XSFM-P3元件数量：1
端子数量：3工作模式：ENHANCEMENT MODE
封装主体材料：UNSPECIFIED封装形状：RECTANGULAR
封装形式：FLANGE MOUNT极性/信道类型：P-CHANNEL
认证状态：Qualified参考标准：MIL-19500/615
表面贴装：NO端子形式：PIN/PEG
端子位置：SINGLE晶体管元件材料：SILICON
Base Number Matches：1

JANSD2N7382 数据手册

 浏览型号JANSD2N7382的Datasheet PDF文件第2页浏览型号JANSD2N7382的Datasheet PDF文件第3页浏览型号JANSD2N7382的Datasheet PDF文件第4页 
TECHNICAL DATA SHEET  
6 Lake Street, Lawrence, MA 01841  
1-800-446-1158 / (978) 620-2600 / Fax: (978) 689-0803  
Website: http: //www.microsemi.com  
RADIATION HARDENED P-CHANNEL MOSFET  
Qualified per MIL-PRF-19500/615  
DEVICES  
LEVELS  
JANSM (3K RAD(Si))  
JANSD (10K RAD(Si))  
JANSR(100K RAD(Si))  
JANSF(300K RAD(Si))  
2N7382  
ABSOLUTE MAXIMUM RATINGS (TC = +25°C unless otherwise noted)  
Parameters / Test Conditions  
Drain – Source Voltage  
Symbol  
VDS  
Value  
-100  
Unit  
Vdc  
Vdc  
Gate – Source Voltage  
VGS  
± 20  
Continuous Drain Current  
ID1  
ID2  
-11.0  
Adc  
Adc  
TC = +25°C  
Continuous Drain Current  
-7.0  
TC = +100°C  
Max. Power Dissipation  
Ptl  
75 (1)  
0.3 (2)  
W
Ω
Drain to Source On State Resistance  
Operating & Storage Temperature  
Rds(on)  
Top, Tstg  
-55 to +150  
°C  
TO-257AA  
Note: (1) Derated Linearly by 0.6 W/°C for TC > +25°C  
JANSM2N7382, JANSD2N7382,  
JANSR2N7382, JANSF2N7382  
See Figure 1  
(2) VGS = -12Vdc, ID = -7.0A  
PRE-IRRADIATION ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise  
noted)  
Parameters / Test Conditions  
Symbol  
Min.  
Max.  
Unit  
Drain-Source Breakdown Voltage  
VGS = 0V, ID = -1mAdc  
V(BR)DSS  
-100  
Vdc  
Gate-Source Voltage (Threshold)  
V
DS ≥ VGS, ID = -1.0mA  
VDS ≥ VGS, ID = -1.0mA, Tj = +125°C  
DS ≥ VGS, ID = -1.0mA, Tj = -55°C  
VGS(th)1  
VGS(th)2  
VGS(th)3  
-2.0  
-1.0  
-4.0  
-5.0  
Vdc  
V
Gate Current  
GS = ±20V, VDS = 0V  
VGS = ±20V, VDS = 0V, Tj = +125°C  
V
IGSS1  
IGSS2  
±100  
±200  
nAdc  
Drain Current  
V
GS = 0V, VDS = -80V  
IDSS1  
IDSS2  
-25  
-0.25  
µAdc  
mAdc  
VGS = 0V, VDS = -80V, Tj = +125°C  
Static Drain-Source On-State Resistance  
VGS = -12V, ID = -7.0A pulsed  
rDS(on)1  
rDS(on)2  
0.3  
0.35  
Ω
Ω
V
GS = -12V, ID = -11.0A pulsed  
Tj = -125°C  
GS = -12V, ID = -7.0A pulsed  
V
rDS(on)3  
0.54  
-3.0  
Ω
Diode Forward Voltage  
VGS = 0V, ID = -11.0A pulsed  
VSD  
Vdc  
T4-LDS-0125 Rev. 1 (091145)  
Page 1 of 4  
1234

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