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J110TA

更新时间： 2024-11-16 13:01:27
品牌 Logo 应用领域
CALOGIC 晶体开关小信号场效应晶体管
页数 文件大小 规格书
1页 25K
描述
Small Signal Field-Effect Transistor, 1-Element, N-Channel, Silicon, Junction FET, TO-92,

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J110TA 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ActiveReach Compliance Code：compliant
HTS代码：8541.21.00.95风险等级：5.68
配置：SINGLE最大漏源导通电阻：18 Ω
FET 技术：JUNCTION最大反馈电容 (Crss)：15 pF
JEDEC-95代码：TO-92JESD-30 代码：O-PBCY-T3
元件数量：1端子数量：3
工作模式：DEPLETION MODE最高工作温度：135 °C
封装主体材料：PLASTIC/EPOXY封装形状：ROUND
封装形式：CYLINDRICAL峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL认证状态：Not Qualified
表面贴装：NO端子形式：THROUGH-HOLE
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

J110TA 数据手册

  
N-Channel JFET Switch  
CORPORATION  
J108 – J110 / SST108 – SST110  
FEATURES  
APPLICATIONS  
Low Cost  
Automated Insertion Package  
Low Insertion Loss  
No Offset or Error Voltages Generated by Closed Switch  
Purely Resistive  
High Isolation Resistance from Driver  
Fast Switching  
Low Noise  
Analog Switches  
Choppers  
Commutators  
•
•
•
•
•
•
•
Low-Noise Audio Amplifiers  
•
ABSOLUTE MAXIMUM RATINGS  
(TA = 25oC unless otherwise specified)  
•
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC  
Operating Temperature Range . . . . . . . . . . . -55oC to +135oC  
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW  
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/oC  
•
PIN CONFIGURATION  
SOT-23  
NOTE: Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to the device. These are  
stress ratings only and functional operation of the device at these or  
any other conditions above those indicated in the operational sections  
of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
G
TO-92  
D
ORDERING INFORMATION  
S
Part  
Package  
Temperature Range  
J108-110  
XJ108-110  
SST109-110 Plastic SOT-23  
Plastic TO-92  
Sorted Chips in Carriers  
-55oC to +135oC  
-55oC to +135oC  
-55oC to +135oC  
G
S
D
PRODUCT MARKING (SOT-23)  
SST108  
SST109  
SST110  
I08  
I09  
I10  
5018  
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)  
108  
109  
110  
SYMBOL  
PARAMETER  
UNITS  
nA  
TEST CONDITIONS  
MIN TYP MAX MIN TYP MAX MIN TYP MAX  
IGSS  
Gate Reverse Current (Note 1)  
Gate-Source Cutoff Voltage  
Gate-Source Breakdown Voltage  
Drain Saturation Current (Note 2)  
Drain Cutoff Current (Note 1)  
Drain-Source ON Resistance  
Drain-Gate OFF Capacitance  
-3  
-3  
-6  
-3  
-4  
VDS = 0V, VGS = -15V  
VDS = 5V, ID = 1µA  
VDS = 0V, IG = -1µA  
VDS = 15V, VGS = 0V  
VDS = 5V, VGS = -10V  
VGS(off)  
BVGSS  
IDSS  
-3  
-25  
80  
-10  
-2  
-25  
40  
-0.5  
-25  
10  
V
mA  
nA  
Ω
ID(off)  
3
8
3
3
rDS(on)  
Cdg(off)  
Csg(off)  
Cdg(on)  
12  
15  
18  
15  
VDS ≤0.1V, VGS = 0V  
15  
VDS = 0,  
VGS = -10V  
(Note 3)  
Source-Gate OFF Capacitance  
15  
85  
15  
85  
15  
85  
pF  
f = 1MHz  
Drain-Gate Plus Source-Gate  
V
DS = VGS = 0  
(Note 3)  
+ Csg(on) ON Capacitance  
td(on)  
tr  
Turn On Delay Time  
Rise Time  
4
1
6
4
1
6
4
1
6
Switching Time Test  
Conditions (Note 3)  
J107  
J109  
1.5V  
-7V  
J110  
1.5V  
-5V  
ns  
td(off)  
Turn OFF Delay Time  
VDD 1.5V  
VGS(off)-12V  
tf  
Fall Time  
30  
30  
30  
RL  
150Ω 150Ω 150Ω  
NOTES: 1. Approximately doubles for every 10oC increase in TA.  
2. Pulse test duration = 300µs; duty cycle ≤3%.  
3. For design reference only, not 100% tested.  
1

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