Datasheet > ISPCLOCK5520

ISPCLOCK5520

更新时间： 2024-11-02 03:25:47

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟发生器
页数	文件大小	规格书
48页	539K
描述
In-System Programmable Clock Generator with Universal Fan-Out Buffer

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数据手册

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ISPCLOCK5520 数据手册

™

ispClock 5500 Family

In-System Programmable Clock Generator

with Universal Fan-Out Buffer

March 2005

Data Sheet

■ Up to Five Clock Frequency Domains

Features

■ Flexible Clock Reference Inputs

• Programmable input standards

- LVTTL, LVCMOS, SSTL, HSTL, LVDS,

LVPECL

■ 10MHz to 320MHz Input/Output Operation

■ Low Output to Output Skew (<50ps)

■ Low Jitter Peak-to-Peak(<70ps)

• Clock A/B selection multiplexer

• Programmable precision termination

■ Up to 20 Programmable Fan-out Buffers

• Programmable output standards and individual

enable controls

■ Four User-programmable Proﬁles Stored in

E²CMOS^®Memory

- LVTTL, LVCMOS, HSTL, SSTL, LVDS,

LVPECL

• Programmable output impedance

- 40 to 70Ω in 5Ω increments

• Programmable slew rate

• Supports both test and multiple operating

conﬁgurations

■ Full JTAG Boundary Scan Test In-System

Programming Support

• Up to 10 banks with individual V

- 1.5V, 1.8V, 2.5V, 3.3V

and GND

CCO

■ Exceptional Power Supply Noise Immunity

■ Commercial (0 to 70°C) and Industrial

■ Fully Integrated High-Performance PLL

• Programmable lock detect

(-40 to 85°C) Temperature Ranges

■ 100-pin and 48-pin TQFP Packages

• Multiply and divide ratio controlled by

- Input divider (5 bits)

- Internal feedback divider (5 bits)

- Five output dividers (5 bits)

• Programmable On-chip Loop Filter

■ Applications

• Circuit board common clock generation and

distribution

• PLL-based frequency generation

• High fan-out clock buffer

■ Precision Programmable Phase Adjustment

(Skew) Per Output

• 16 settings; minimum step size 195ps

- Locked to VCO frequency

• Up to +/- 12ns skew range

• Coarse and ﬁne adjustment modes

Product Family Block Diagram

LOCK DETECT

OUTPUT

DIVIDERS

SKEW

CONTROL

OUTPUT

DRIVERS

BYPASS

MUX

PHASE/

FREQUENCY

DETECTOR

FILTER

VCO

OUTPUT

ROUTING

MATRIX

PLL CORE

JTAG

INTERFACE

E CMOS

MEMORY

Multiple Profile

Management Logic

INTERNAL FEEDBACK PATH

* Input Available only on ispClock 5520

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

clk5500_06.2

12 3 4 5 6 7...48

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与ISPCLOCK5520相关器件

型号	品牌	获取价格	描述	数据表
ISPCLOCK5600	LATTICE	获取价格	In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5600A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5610A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5620A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPD03N60C3	ISC	获取价格	N-Channel MOSFET Transistor
ISPD06N60C3	ISC	获取价格	N-Channel MOSFET Transistor
ISPD60	ETC	获取价格	DARLINGTON-NPN-OUTPUT DC-INPUT OPTOCOUPLER
ISPD60_10	ISOCOM	获取价格	NON BASE LEAD OPTICALLY COUPLED ISOLATOR PHOTODARLINGTON OUTPUT
ISPD60G	ISOCOM	获取价格	Darlington Output Optocoupler, 1-Element, 5300V Isolation, ROHS COMPLIANT, PLASTIC, DIP-6
ISPD60-G	ISOCOM	获取价格	Darlington Output Optocoupler, 1-Element, 5300V Isolation, ROHS COMPLIANT, PLASTIC, DIP-6

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