Datasheet > ISPCLOCK5620A

ISPCLOCK5620A

更新时间： 2024-11-02 03:25:47

品牌	Logo	应用领域
莱迪思 - LATTICE		时钟发生器
页数	文件大小	规格书
51页	980K
描述
In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer

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ISPCLOCK5620A 数据手册

™

ispClock 5600A Family

In-System Programmable, Enhanced Zero-Delay

Clock Generator with Universal Fan-Out Buffer

June 2008

Data Sheet DS1019

■ Up to Five Clock Frequency Domains

■ Flexible Clock Reference and External

Feedback Inputs

Features

■ 8MHz to 400MHz Input/Output Operation

■ Low Output to Output Skew (<50ps)

■ Low Jitter Peak-to-Peak

■ Up to 20 Programmable Fan-out Buffers

• Programmable output standards and individual

enable controls

• Programmable input standards

- LVTTL, LVCMOS, SSTL, HSTL, LVDS,

LVPECL, Differential HSTL, SSTL

• Clock A/B selection multiplexer

• Feedback A/B selection multiplexer

• Programmable termination

- LVTTL, LVCMOS, HSTL, eHSTL, SSTL,

LVDS, LVPECL, Differential HSTL, SSTL

• Programmable output impedance

- 40 to 70Ω in 5Ω increments

• Programmable slew rate

• Up to 10 banks with individual V

- 1.5V, 1.8V, 2.5V, 3.3V

■ All Inputs and Outputs are Hot Socket

Compliant

■ Four User-programmable Proﬁles Stored in

E²CMOS^®Memory

and GND

• Supports both test and multiple operating

conﬁgurations

CCO

■ Fully Integrated High-Performance PLL

• Programmable lock detect

■ Full JTAG Boundary Scan Test In-System

Programming Support

• Multiply and divide ratio controlled by

- Input divider (1 to 40)

- Feedback divider (1 to 40)

- Five output dividers (2 to 80)

• Programmable on-chip loop ﬁlter

• Compatible with spread spectrum clocks

■ Exceptional Power Supply Noise Immunity

■ Commercial (0 to 70°C) and Industrial

(-40 to 85°C) Temperature Ranges

■ 100-pin and 48-pin TQFP Packages

■ Applications

• Circuit board common clock generation and

distribution

■ Precision Programmable Phase Adjustment

(Skew) Per Output

• PLL-based frequency generation

• High fan-out clock buffer

• Zero-delay clock buffer

• 16 settings; minimum step size 156ps

- Locked to VCO frequency

• Up to +/- 12ns skew range

• Coarse and ﬁne adjustment modes

Product Family Block Diagram

LOCK DETECT

OUTPUT

DIVIDERS

SKEW

CONTROL

OUTPUT

DRIVERS

BYPASS

MUX

PHASE/

FREQUENCY

DETECTOR

FILTER

VCO

OUTPUT

ROUTING

MATRIX

PLL CORE

Internal/External

Feedback

JTAG

INTERFACE

E CMOS

MEMORY

Multiple Profile

Management Logic

Select

INTERNAL FEEDBACK PATH

* Input Available only on ispClock5620A

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

DS1019_01.4

12 3 4 5 6 7...51

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