Datasheet > ISPCLOCK5308S

ISPCLOCK5308S

更新时间： 2024-01-27 23:38:30

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
56页	1243K
描述
In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended

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ISPCLOCK5308S 数据手册

™

ispClock 5300S Family

In-System Programmable, Zero-Delay

Universal Fan-Out Buffer, Single-Ended

October 2007

Preliminary Data Sheet DS1010

• Up to +/- 5ns skew range

• Coarse and ﬁne adjustment modes

Features

■ Four Operating Conﬁgurations

■ Up to Three Clock Frequency Domains

• Zero delay buffer

• Zero delay and non-zero delay buffer

• Dual non-zero delay buffer

• Non-zero delay buffer with output divider

■ Flexible Clock Reference and External

Feedback Inputs

• Programmable single-ended or differential input

reference standards

■ 8MHz to 267MHz Input/Output Operation

■ Low Output to Output Skew (<100ps)

■ Low Jitter Peak-to-Peak (< 70 ps)

- LVTTL, LVCMOS, SSTL, HSTL, LVDS,

LVPECL, Differential HSTL, Differential

SSTL

• Clock A/B selection multiplexer

• Programmable Feedback Standards

- LVTTL, LVCMOS, SSTL, HSTL

• Programmable termination

■ Up to 20 Programmable Fan-out Buffers

• Programmable single-ended output standards

and individual enable controls

- LVTTL, LVCMOS, HSTL, eHSTL, SSTL

• Programmable output impedance

- 40 to 70Ω in 5Ω increments

■ All Inputs and Outputs are Hot Socket

Compliant

• Programmable slew rate

• Up to 10 banks with individual V

- 1.5V, 1.8V, 2.5V, 3.3V

■ Full JTAG Boundary Scan Test In-System

and GND

CCO

Programming Support

■ Exceptional Power Supply Noise Immunity

■ Fully Integrated High-Performance PLL

• Programmable lock detect

■ Commercial (0 to 70°C) and Industrial

(-40 to 85°C) Temperature Ranges

• Three “Power of 2” output dividers (5-bit)

• Programmable on-chip loop ﬁlter

• Compatible with spread spectrum clocks

• Internal/external feedback

■ 48-pin and 64-pin TQFP Packages

■ Applications

• Circuit board common clock distribution

• PLL-based frequency generation

• High fan-out clock buffer

■ Precision Programmable Phase Adjustment

(Skew) Per Output

• Zero-delay clock buffer

• 8 settings; minimum step size 156ps

- Locked to VCO frequency

ispClock5300S Family Functional Diagram

LOCK

PLL_BYPASS

REFA /

REFP

SKEW

CONTROL

OUTPUT

DRIVERS

OUTPUT

DIVIDERS

REFB /

REFN

OUTPUT 1

5-Bit

PHASE

FREQ.

DETECT

LOOP

FILTER

VCO

5-bit

REFSEL

FBK

OUTPUT

ROUTING

MATRIX

OUTPUT N

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

DS1010_01.4

12 3 4 5 6 7...56

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与ISPCLOCK5308S相关器件

型号	品牌	获取价格	描述	数据表
ISPCLOCK5312S	LATTICE	获取价格	In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPCLOCK5316S	LATTICE	获取价格	In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPCLOCK5320S	LATTICE	获取价格	In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPCLOCK5500	LATTICE	获取价格	In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5510	LATTICE	获取价格	In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5520	LATTICE	获取价格	In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5600	LATTICE	获取价格	In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5600A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5610A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPCLOCK5620A	LATTICE	获取价格	In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer

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