Dual LDO with Low Noise, Very High PSRR and Low I
Q
ISL78302A
ISL78302A is a high-performance dual LDO capable of
sourcing 300mA current from each output. It has a low
standby current and very high PSRR and is stable with output
capacitance of 1µF to 10µF with ESR of up to 200mΩ.
Features
• Integrates Two 300mA High-performance LDOs
• Excellent Transient Response to Large Current Steps
• ±1.8% Accuracy Over All Operating Conditions
• Excellent Load Regulation: < 0.1% Voltage Change Across
Full Range of Load Current
The device integrates an individual power-on-reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise-filtering capacitor for low noise and
high-PSRR applications.
• Low Output Noise: Typically 30µV
• Very High PSRR: 90dB @ 1kHz
@ 100µA (1.5V)
RMS
• Extremely Low Quiescent Current: 47µA (Both LDOs Active)
• Wide Input Voltage Capability: 2.3V to 6.5V
• Low Dropout Voltage: Typically 230mV @ 300mA
• Stable with 1µF to 10µF Ceramic Capacitors
• Separate Enable and POR Pins for Each LDO
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate Enable pins control each
individual LDO output. When both Enable pins are low, the
device is in shutdown, typically drawing less than 0.3µA.
• Soft-start and Staged Turn-on to Limit Input Current Surge
During Enable
The ISL78302A is AEC - Q100 rated. The ISL78302A is rated
for the automotive temperature range (-40°C to +105°C).
• Current Limit and Overheat Protection
• Tiny 10 Ld 3mmx3mm DFN Package
• -40°C to +105°C Operating Temperature Range
• Pb-free (RoHS Compliant)
• AEC - Q100 Tested
Applications
• Radio Receivers
• Camera Modules
• GPS/Navigation
• Infotainment Systems
ISL78302A
10
9
1
2
VIN (2.3 TO 6.5V)
ENABLE1
V
VIN
VO1
VO2
OUT1
ON
ON
EN1
V
OUT2
V
OK
OUT2
OFF
ENABLE2
OFF
8
7
3
4
EN2
POR2
POR1
RESET2
(200ms DELAY,
C3 = 0.01µF)
V
V
TOO LOW
OUT2
V
CBYP
OK
OUT1
6
5
CPOR
GND
RESET1
(2ms DELAY)
TOO LOW
C1
C2
C3
C4
C5
OUT1
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
FIGURE 1. TYPICAL APPLICATION
December 23, 2013
FN7932.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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