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ISL78302AARJRZ-T7A

更新时间： 2024-01-24 10:00:48
品牌 Logo 应用领域
瑞萨 - RENESAS PC输出元件调节器
页数 文件大小 规格书
12页 660K
描述
Dual LDO with Low Noise, Very High PSRR and Low IQ

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ISL78302AARJRZ-T7A 技术参数

生命周期：Active零件包装代码：DFN
针数：10Reach Compliance Code：compliant
风险等级：2.04Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：5494090
Samacsys Pin Count：11Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline No-leadSamacsys Footprint Name：L10.3x3C-
Samacsys Released Date：2019-12-26 14:10:42Is Samacsys：N
调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATORBase Number Matches：1

ISL78302AARJRZ-T7A 数据手册

 浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第2页浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第3页浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第4页浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第5页浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第6页浏览型号ISL78302AARJRZ-T7A的Datasheet PDF文件第7页 
DATASHEET  
ISL78302A  
Dual LDO with Low Noise, Very High PSRR and Low IQ  
FN7932  
Rev 2.00  
December 22, 2015  
ISL78302A is a high-performance dual LDO capable of  
sourcing 300mA current from each output. It has a low  
standby current and very high PSRR and is stable with output  
capacitance of 1µF to 10µF with ESR of up to 200mΩ.  
Features  
• Integrates Two 300mA High-performance LDOs  
• Excellent Transient Response to Large Current Steps  
• ±1.8% Accuracy Over All Operating Conditions  
The device integrates an individual Power-On Reset (POR)  
function for each output. The POR delay for VO2 can be  
externally programmed by connecting a timing capacitor to the  
CPOR pin. The POR delay for VO1 is internally fixed at  
approximately 2ms. A reference bypass pin is also provided for  
connecting a noise-filtering capacitor for low noise and  
high-PSRR applications.  
• Excellent Load Regulation: < 0.1% Voltage Change Across  
Full Range of Load Current  
• Low Output Noise: Typically 30µV  
• Very High PSRR: 90dB at 1kHz  
at 100µA (1.5V)  
RMS  
• Extremely Low Quiescent Current: 47µA (Both LDOs Active)  
• Wide Input Voltage Capability: 2.3V to 6.5V  
The quiescent current is typically only 47µA with both LDOs  
enabled and active. Separate Enable pins control each  
individual LDO output. When both Enable pins are low, the  
device is in shutdown, typically drawing less than 0.3µA.  
• Low Dropout Voltage: Typically 230mV at 300mA  
• Stable with 1µF to 10µF Ceramic Capacitors  
• Separate Enable and POR Pins for Each LDO  
The ISL78302A is AEC-Q100 qualified. The ISL78302A is rated  
for the automotive temperature range (-40°C to +105°C).  
• Soft-start and Staged Turn-on to Limit Input Current Surge  
During Enable  
• Current Limit and Overheat Protection  
• Tiny 10 Ld 3mmx3mm DFN Package  
• -40°C to +105°C Operating Temperature Range  
• Pb-free (RoHS Compliant)  
• AEC-Q100 Qualified  
Applications  
• Radio Receivers  
• Camera Modules  
• GPS/Navigation  
• Infotainment Systems  
ISL78302A  
10  
1
2
VIN (2.3 TO 6.5V)  
ENABLE1  
V
VIN  
VO1  
VO2  
OUT1  
ON  
ON  
9
EN1  
V
OUT2  
V
OK  
OUT2  
OFF  
ENABLE2  
OFF  
8
7
3
4
EN2  
POR2  
POR1  
RESET2  
(200ms DELAY,  
C3 = 0.01µF)  
V
V
TOO LOW  
OUT2  
V
CBYP  
OK  
OUT1  
6
5
CPOR  
GND  
RESET1  
(2ms DELAY)  
TOO LOW  
C1  
C2  
C3  
C4  
C5  
OUT1  
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR  
C2: 0.1µF X7R CERAMIC CAPACITOR  
C3: 0.01µF X7R CERAMIC CAPACITOR  
FIGURE 1. TYPICAL APPLICATION  
FN7932 Rev 2.00  
December 22, 2015  
Page 1 of 12  
1234567...12

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