DATASHEET
Dual LDO with Low Noise, High Performance and Low I
Q
ISL78302
ISL78302 is a high performance dual LDO capable of sourcing
300mA current from each output. It has a low standby current
and is stable with an output capacitance of 1µF to 10µF and an
ESR of up to 200mΩ.
Features
• Integrates two 300mA high performance LDOs
• Excellent transient response to large current steps
• ±1.8% Accuracy over all operating conditions
• Excellent load regulation: <0.1% voltage change across full
range of load current
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be externally
programmed by connecting a timing capacitor to the CPOR pin.
The POR delay for VO1 is internally fixed at approximately 2ms. A
reference bypass pin is also provided for connecting a noise
filtering capacitor for low noise and high-PSRR applications.
• Extremely low quiescent current: 47µA (both LDOs active)
• Wide input voltage capability: 2.3V to 6.5V
• Low dropout voltage: typically 300mV at 300mA
• Low output noise: typically 37µV
at 100µA (1.5V)
RMS
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate enable pins control each individual
LDO output. When both enable pins are low, the device is in
shutdown, typically drawing less than 0.5µA.
• Stable with 1µF to 10µF ceramic capacitors
• Separate enable and POR pins for each LDO
• Soft-start and staged turn-on to limit input current surge during
enable
The part operates down to 2.3V and up to 6.5V input. The typical
output voltage can be as low as 1.2V and as high as 3.3V for
each regulator. Please refer to the “Ordering Information” on
page 3 for standard options.
• Current limit and over-temperature protection
• Tiny 10 Lead 3mm x 3mm DFN package
• AEC-Q100 qualified
The ISL78302 is AEC-Q100 qualified at the automotive
temperature range of -40°C to +105°C.
• Pb-free (RoHS Compliant)
Applications
• Radio receivers
• Camera modules
• GPS/navigation
• Infotainment systems
ISL78302
10
1
VIN (2.3 TO 6.5V)
V
VIN
VO1
OUT1
ON
ON
9
2
EN1
VO2
V
ENABLE1
ENABLE2
OUT2
V
OK
OUT2
OFF
OFF
8
7
3
4
EN2
POR2
POR1
RESET2
(200ms DELAY,
C3 = 0.01µF)
V
V
TOO LOW
OUT2
V
CBYP
OK
OUT1
6
5
CPOR
GND
RESET1
(2ms DELAY)
TOO LOW
C1
C2
C3
C4
C5
OUT1
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
FIGURE 1. TYPICAL APPLICATION
November 6, 2014
FN7696.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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