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ISL705BEHVX PDF预览

ISL705BEHVX

更新时间： 2024-01-04 01:20:09
品牌 Logo 应用领域
英特矽尔 - INTERSIL 信息通信管理
页数 文件大小 规格书
19页 1152K
描述
Rad-Hard, 5.0V/3.3V μ-Processor Supervisory Circuits

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ISL705BEHVX 技术参数

生命周期：Transferred包装说明：DIE,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.66
其他特性：RESET THRESHOLD VOLTAGE IS 4.65可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-XUUC-N10
信道数量：1功能数量：1
端子数量：10最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：RECTANGULAR
封装形式：UNCASED CHIP最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：NO LEAD
端子位置：UPPER总剂量：100k Rad(Si) V
Base Number Matches：1

ISL705BEHVX 数据手册

 浏览型号ISL705BEHVX的Datasheet PDF文件第1页浏览型号ISL705BEHVX的Datasheet PDF文件第3页浏览型号ISL705BEHVX的Datasheet PDF文件第4页浏览型号ISL705BEHVX的Datasheet PDF文件第5页浏览型号ISL705BEHVX的Datasheet PDF文件第6页浏览型号ISL705BEHVX的Datasheet PDF文件第7页 
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH  
Pin Configurations  
ISL705AEH, ISL706AEH  
(8 LD FLATPACK)  
TOP VIEW  
ISL705BEH, ISL706BEH  
(8 LD FLATPACK)  
TOP VIEW  
ISL705CEH, ISL706CEH  
(8 LD FLATPACK)  
TOP VIEW  
MR  
WDO  
RST  
WDI  
PFO  
MR  
WDO  
RST_OD  
WDI  
MR  
1
2
3
4
8
7
6
5
WDO  
RST  
WDI  
PFO  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
V
DD  
GND  
PFI  
DD  
GND  
PFI  
DD  
GND  
PFI  
PFO  
Pin Descriptions  
ISL705AEH  
ISL705BEH  
ISL705CEH  
ISL706CEH  
ISL706AEH  
ISL706BEH  
NAME  
MR  
DESCRIPTION  
1
2
1
2
1
Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may  
be used to trigger a reset pulse.  
2
V
Power Supply. V is a supply voltage input that provides power to all internal circuitry.  
DD  
This input is also monitored and used to trigger a reset pulse. Reset is guaranteed  
DD  
operable after V rises above 1.2V.  
DD  
3
4
3
4
3
4
GND  
PFI  
Ground. GND is a supply voltage return for all internal circuitry. This return establishes  
the reference level for voltage detection and should be connected to signal ground.  
Power Fail Input. PFI is an input to a threshold detector, which may be used to monitor  
another supply voltage level. The threshold of the detector (V ) is 1.25V in the  
PFI  
ISL705AEH/BEH/CEH and 0.6V in the ISL706AEH/BEH/CEH.  
5
6
5
6
5
6
PFO  
WDI  
Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that  
indicates the voltage at the PFI pin is less than V  
.
PFI  
Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the  
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes  
low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared  
and will not count. As soon as reset is released and WDI is driven high or low, the timer  
will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer  
disables the watchdog feature.  
7
-
-
RST  
Reset. RST is an active-low, push-pull output that is guaranteed to be low once V  
DD  
reaches 1.2V. As V rises, RST stays low. When V rises above a 4.65V  
DD DD  
(ISL705AEH/BEH/CEH) or 3.08V (ISL706AEH/BEH/CEH) reset threshold, an internal  
timer releases RST after about 200ms. RST pulses low whenever V goes below the  
DD  
reset threshold. If a brownout condition occurs in the middle of a previously initiated  
reset pulse, the pulse will continue for at least 140ms. On power-down, once V falls  
DD  
below the reset threshold, RST goes low and is guaranteed low until V drops below  
DD  
1.2V.  
-
-
7
-
-
RST  
Reset. RST is an active-high, push-pull output. RST is the inverse of RST.  
7
RST_OD Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.  
This pin may be pulled up to V with a resistor consistent with the sink and leakage  
DD  
current specifications of the output. Behavior is otherwise identical to the RST pin.  
8
8
8
WDO  
Watchdog Output. WDO is an active-low, push-pull output that goes low if the  
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is  
usually connected to the non-maskable interrupt input of a microprocessor. When V  
DD  
drops below the reset threshold, WDO will go low whether or not the watchdog timer  
has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since  
floating WDI disables the internal timer, WDO goes low only when V drops below the  
DD  
reset threshold, thus functioning as a low line output.  
FN8262.0  
March 30, 2012  
2
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