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ISL705BEHVX PDF预览

ISL705BEHVX

更新时间: 2024-02-07 00:01:16
品牌 Logo 应用领域
英特矽尔 - INTERSIL 信息通信管理
页数 文件大小 规格书
19页 1152K
描述
Rad-Hard, 5.0V/3.3V μ-Processor Supervisory Circuits

ISL705BEHVX 技术参数

生命周期:Transferred包装说明:DIE,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.66
其他特性:RESET THRESHOLD VOLTAGE IS 4.65可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码:R-XUUC-N10
信道数量:1功能数量:1
端子数量:10最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:RECTANGULAR
封装形式:UNCASED CHIP最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子形式:NO LEAD
端子位置:UPPER总剂量:100k Rad(Si) V
Base Number Matches:1

ISL705BEHVX 数据手册

 浏览型号ISL705BEHVX的Datasheet PDF文件第13页浏览型号ISL705BEHVX的Datasheet PDF文件第14页浏览型号ISL705BEHVX的Datasheet PDF文件第15页浏览型号ISL705BEHVX的Datasheet PDF文件第16页浏览型号ISL705BEHVX的Datasheet PDF文件第17页浏览型号ISL705BEHVX的Datasheet PDF文件第18页 
ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH  
Package Outline Drawing  
K8.A  
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
Rev 2, 12/10  
PIN NO. 1  
ID OPTIONAL  
0.015 (0.38)  
0.008 (0.20)  
1
2
0.050 (1.27 BSC)  
0.005 (0.13)  
0.265 (6.73)  
0.245 (6.22)  
MIN  
PIN NO. 1  
ID AREA  
4
0.022 (0.56)  
0.015 (0.38)  
TOP VIEW  
0.115 (2.92)  
0.070 (1.18)  
0.045 (1.14)  
0.026 (0.66)  
0.09 (0.23)  
0.04 (0.10)  
6
0.265 (6.75)  
0.245 (6.22)  
-D-  
-H-  
-C-  
0.180 (4.57)  
0.170 (4.32)  
0.370 (9.40)  
0.250 (6.35)  
SEATING AND  
BASE PLANE  
0.03 (0.76) MIN  
SIDE VIEW  
0.007 (0.18)  
0.004 (0.10)  
NOTES:  
LEAD FINISH  
Index area: A notch or a pin one identification mark shall be located  
adjacent to pin one and shall be located within the shaded area shown.  
The manufacturer’s identification shall not be used as a pin one  
identification mark. Alternately, a tab may be used to identify pin one.  
1.  
0.009 (0.23)  
0.004 (0.10)  
BASE  
METAL  
2. If a pin one identification mark is used in addition to a tab, the limits  
of the tab dimension do not apply.  
0.019 (0.48)  
0.015 (0.38)  
3. The maximum limits of lead dimensions (section A-A) shall be  
measured at the centroid of the finished lead surfaces, when solder  
dip or tin plate lead finish is applied.  
0.0015 (0.04)  
MAX  
0.022 (0.56)  
0.015 (0.38)  
4. Measure dimension at all four corners.  
3
5. For bottom-brazed lead packages, no organic or polymeric materials  
shall be molded to the bottom of the package to cover the leads.  
SECTION A-A  
6. Dimension shall be measured at the point of exit (beyond the  
meniscus) of the lead from the body. Dimension minimum shall  
be reduced by 0.0015 inch (0.038mm) maximum when solder dip  
lead finish is applied.  
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
8. Controlling dimension: INCH.  
FN8262.0  
March 30, 2012  
19  

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