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ISL70001ASEH

更新时间： 2024-01-22 08:19:41
品牌 Logo 应用领域
英特矽尔 - INTERSIL 稳压器
页数 文件大小 规格书
25页 1511K
描述
Rad Hard and SEE Hard 6A Synchronous Buck Regulator

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中文翻译

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ISL70001ASEH 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：DIE包装说明：DIE,
针数：34Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.65Is Samacsys：N
其他特性：OPERATES IN ADJUSTABLE MODE FROM 0.8V TO 4.675V模拟集成电路 - 其他类型：SWITCHING REGULATOR
控制模式：CURRENT-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：5.5 V最小输入电压：3 V
标称输入电压：3.6 VJESD-30 代码：R-XUUC-N34
JESD-609代码：e4功能数量：1
端子数量：34最高工作温度：125 °C
最低工作温度：-55 °C最大输出电流：6 A
标称输出电压：1.8 V封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：RECTANGULAR
封装形式：UNCASED CHIP峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified筛选级别：MIL-PRF-38535
表面贴装：YES切换器配置：BUCK
最大切换频率：1200 kHz温度等级：MILITARY
端子面层：Gold (Au)端子形式：NO LEAD
端子位置：UPPER处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

ISL70001ASEH 数据手册

 浏览型号ISL70001ASEH的Datasheet PDF文件第1页浏览型号ISL70001ASEH的Datasheet PDF文件第2页浏览型号ISL70001ASEH的Datasheet PDF文件第4页浏览型号ISL70001ASEH的Datasheet PDF文件第5页浏览型号ISL70001ASEH的Datasheet PDF文件第6页浏览型号ISL70001ASEH的Datasheet PDF文件第7页 
ISL70001ASEH  
Pin Configuration  
ISL70001ASEH  
(48 LD CQFP)  
TOP VIEW  
6
5
4
3
2
1
48 47 46 45 44 43  
42  
PVIN3  
LX3  
7
M/S  
ZAP  
TDI  
41  
40  
39  
38  
37  
8
PGND3  
PGND3  
PGND4  
PGND4  
LX4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
TDO  
PGOOD  
SS  
* HEATSINK  
36  
35  
34  
33  
32  
31  
DVDD  
DVDD  
DGND  
DGND  
AGND  
AGND  
PVIN4  
PVIN4  
PVIN5  
PVIN5  
LX5  
19 20 21 22 23 24 25 26 27 28 29 30  
* Heatsink available in R48.B package  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
DESCRIPTION  
1, 2, 27, 28, 29, 30,  
37, 38, 39, 40, 47,  
48  
PGNDx  
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins  
directly to the ground plane. These pins should also connect to the negative terminals of the input and output  
capacitors. Locate the input and output capacitors as close as possible to the IC.  
3, 26, 31, 36, 41,  
46  
LXx  
These pins are the outputs of the corresponding internal power blocks and should be connected to the output  
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize  
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The  
Schottky diode should be located as close as possible to the IC.  
4, 5, 24, 25, 32, 33,  
34, 35, 42, 43, 44,  
45  
PVINx  
SYNC  
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be  
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly  
to PGNDx with ceramic capacitors located as close as possible to the IC.  
6
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the  
SYNC input of another ISL70001ASEH. When configured as an input (Slave Mode), this pin accepts the SYNC  
output from another ISL70001ASEH or an external clock. Synchronization of the slave unit is 180° out-of-phase  
with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the  
frequency must be within the range of 1MHz ±20%.  
7
M/S  
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output  
(Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.  
8
9
ZAP  
TDI  
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.  
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.  
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.  
10  
11  
TDO  
PGOOD  
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output  
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,  
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin  
to DGND with a 10nF ceramic capacitor to mitigate SEE.  
FN8365.0  
May 22, 2013  
3
1234567...25

中文翻译

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