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ISL6620ACBZ PDF预览

ISL6620ACBZ

更新时间： 2024-02-28 21:01:41
品牌 Logo 应用领域
英特矽尔 - INTERSIL 驱动器接口集成电路光电二极管
页数 文件大小 规格书
10页 221K
描述
VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

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ISL6620ACBZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.34
高边驱动器：YES接口集成电路类型：AND GATE BASED MOSFET DRIVER
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：3
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
标称输出峰值电流：4 A封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：MOSFET Drivers最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

ISL6620ACBZ 数据手册

 浏览型号ISL6620ACBZ的Datasheet PDF文件第4页浏览型号ISL6620ACBZ的Datasheet PDF文件第5页浏览型号ISL6620ACBZ的Datasheet PDF文件第6页浏览型号ISL6620ACBZ的Datasheet PDF文件第8页浏览型号ISL6620ACBZ的Datasheet PDF文件第9页浏览型号ISL6620ACBZ的Datasheet PDF文件第10页 
ISL6620, ISL6620A  
improvement suggestions. The total gate drive power losses  
Power-On Reset (POR) Function  
due to the gate charge of MOSFETs and the driver’s internal  
circuitry and their corresponding average driver current can  
be estimated using Equations 2 and 3, respectively:  
During initial start-up, the VCC voltage rise is monitored. Once  
the rising VCC voltage exceeds 3.8V (typically), operation of  
the driver is enabled and the PWM input signal takes control  
of the gate drives. If VCC drops below the falling threshold of  
3.5V (typically), operation of the driver is disabled.  
(EQ. 2)  
P
= P  
+ P  
+ I • VCC  
Q
Qg_TOT  
Qg_Q1  
Qg_Q2  
2
Q
• UVCC  
G1  
Internal Bootstrap Device  
---------------------------------------  
P
=
• F  
• N  
• N  
Qg_Q1  
SW  
Q1  
V
GS1  
ISL6620, ISL6620A features an internal bootstrap Schottky  
diode. Simply adding an external capacitor across the BOOT  
and PHASE pins completes the bootstrap circuit. The  
bootstrap function is also designed to prevent the bootstrap  
capacitor from overcharging due to the large negative swing  
at the trailing-edge of the PHASE node. This reduces  
voltage stress on the BOOT to PHASE pins.  
2
Q
• LVCC  
G2  
--------------------------------------  
P
=
• F  
Qg_Q2  
SW  
Q2  
V
GS2  
Q
• UVCC • N  
Q
• LVCC • N  
G2 Q2  
⎛
⎜
⎝
⎞
⎟
⎠
G1  
Q1  
----------------------------------------------------- ----------------------------------------------------  
I
=
+
• F  
+ I  
DR  
SW  
Q
V
V
GS2  
GS1  
(EQ. 3)  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
where the gate charge (Q and Q ) is defined at a  
G1  
G2  
particular gate to source voltage (V  
and V  
) in the  
GS1  
GS2  
corresponding MOSFET data sheet; I is the driver’s total  
Q
quiescent current with no load at both drive outputs; N  
and N are number of upper and lower MOSFETs,  
Q2  
respectively; UVCC and LVCC are the drive voltages for  
Q1  
both upper and lower FETs, respectively. The I VCC  
Q*  
Q
= 100nC  
product is the quiescent power of the driver without a load.  
GATE  
0.4  
0.2  
0.0  
50nC  
P
P
= P  
+ P  
+ I • VCC  
(EQ. 4)  
DR  
DR_UP  
DR_LOW  
Q
20nC  
R
R
P
Qg_Q1  
⎛
⎞
HI1  
LO1  
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0  
ΔV (V)  
-------------------------------------- --------------------------------------- ---------------------  
=
+
•
⎜
⎝
⎟
DR_UP  
R
+ R  
R
+ R  
EXT1  
2
BOOT_CAP  
⎠
HI1  
EXT1  
LO1  
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE  
VOLTAGE  
R
R
P
Qg_Q2  
⎛
⎜
⎝
⎞
HI2  
LO2  
-------------------------------------- --------------------------------------- ---------------------  
P
R
=
+
•
⎟
DR_LOW  
R
+ R  
R
+ R  
⎠
EXT2  
2
HI2  
EXT2  
LO2  
The bootstrap capacitor must have a maximum voltage  
rating well above the maximum voltage intended for VCC. Its  
capacitance value can be estimated using Equation 1:  
R
R
GI1  
GI2  
-------------  
-------------  
= R  
+
R
= R +  
G2  
EXT1  
G1  
EXT2  
N
N
Q1  
Q2  
Q
GATE  
-------------------------------------  
C
≥
BOOT_CAP  
ΔV  
BOOT_CAP  
The total gate drive power losses are dissipated among the  
resistive components along the transition path, as outlined in  
Equation 4. The drive resistance dissipates a portion of the  
total gate drive power losses, the rest will be dissipated by the  
external gate resistors (R and R ) and the internal gate  
(EQ. 1)  
Q
• VCC  
G1  
V
-------------------------------  
Q
=
• N  
Q1  
GATE  
GS1  
where Q is the amount of gate charge per upper MOSFET  
G1  
G1  
G2  
at V  
gate-source voltage and N is the number of  
resistors (R  
and R ) of MOSFETs. Figures 3 and 4 show  
GS1  
control MOSFETs. The ΔV  
Q1  
GI1  
GI2  
term is defined as the  
the typical upper and lower gate drives turn-on current paths.  
BOOT_CAP  
allowable droop in the rail of the upper gate drive. Select  
UVCC  
BOOT  
results are exemplified in Figure 2.  
D
Power Dissipation  
C
GD  
Package power dissipation is mainly a function of the  
switching frequency (F ), the output drive impedance, the  
R
HI1  
G
C
SW  
DS  
layout resistance, and the selected MOSFET’s internal gate  
R
R
LO1  
R
G1  
C
L1  
resistance and total gate charge (Q ). Calculating the power  
G
GS  
Q1  
dissipation in the driver for a desired application is critical to  
ensure safe operation. Exceeding the maximum allowable  
power dissipation level may push the IC beyond the maximum  
recommended operating junction temperature. The DFN  
package is more suitable for high frequency applications. See  
“Layout Considerations” on page 8 for thermal impedance  
S
PHASE  
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH  
FN6494.0  
April 25, 2008  
7
1...45678910

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