ISL6532A
®
Data Sheet
August 2004
FN9099.3
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
Features
• Generates 3 Regulated Voltages
The ISL6532A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
and integrated LDO to supply V
with high current during
DDQ
- Glitch-free Transitions During State Changes
- LDO Regulator for 1.5V Video and Core voltage
S0/S1 states and standby current during S3 state. During
S0/S1 state, a fully integrated sink-source regulator
generates an accurate (V
/2) high current V voltage
• ACPI compliant sleep state control
DDQ
TT
without the need for a negative supply. A buffered version of
the V /2 reference is provided as V . An LDO
controller is also integrated for AGP core voltage regulation.
• Integrated V
REF
Buffer
DDQ REF
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and standby LDO provide a maximum static
regulation tolerance of ±2% over line, load, and temperature
ranges. The output is user-adjustable by means of external
resistors down to 0.8V.
- All Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator
Switching memory core output between the PWM regulator
and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the PGOOD signal
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-free available
indicates V is within spec and operational.
TT
Each output is monitored for under and over-voltage events.
The switching regulator has over current protection. Thermal
shutdown is integrated.
Applications
•
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Pinout
ISL6532A (QFN) TOP VIEW
•
Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
28
27
26
25
24
23
22
GNDP
5VSBY
GNDQ
GNDQ
VTT
1
2
3
4
5
6
7
21 PGOOD
Ordering Information
20
19
PHASE
DRIVE2
TEMP. RANGE
o
PKG.
DWG. #
PART NUMBER
( C)
PACKAGE
GND
29
18 FB2
ISL6532ACR
0 to 70
0 to 70
28 Ld 6x6 QFN
L28.6x6
L28.6x6
ISL6532ACRZ
(See Note)
28 Ld 6x6 QFN
(Pb-free)
17
16
15
GNDA
COMP
FB
VTT
*Add “-T” suffix to part number for tape and reel packaging.
VDDQ
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
8
9
10
11
12
13
14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
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