ISL6532B
®
Data Sheet
July 2004
FN9120.3
ACPI Regulator/Controller for
Features
Dual Channel DDR Memory Systems
• Generates 2 Regulated Voltages
The ISL6532B provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate V
/2 Divider Reference
DDQ
and integrated LDO to supply V
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
with high current during
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
DDQ
• Integrated V
REF
Buffer
an accurate (V
/2) high current V voltage without the
DDQ
TT
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
need for a negative supply. A buffered version of the V
/2
DDQ
reference is provided as V
.
REF
• Tight Output Voltage Regulation
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
- Both Outputs: ±2% Over Temperature
topology. The synchronous buck converter uses voltage-
• 5V or 3.3V Down Conversion
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of ±2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection on V and Under/Over-Voltage
TT
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
An integrated soft-start feature brings V
DDQ
into regulation
in a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD
signal indicates that all supplies are within spec and
operational.
• Pb-free available
Applications
•
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Each output is monitored for under and over-voltage events.
Current limiting is included on the V and V
standby
TT
DDQ
regulators. Thermal shutdown is integrated.
•
Graphics cards - GPU and memory supplies
• ASIC power supplies
Pinout
ISL6532B (QFN)
TOP VIEW
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
20 19 18 17 16
5VSBY
GND
VTT
NCH
TEMP. RANGE
o
1
2
3
4
5
15
14
13
12
11
PART NUMBER
( C)
PACKAGE
PKG. DWG. #
PGOOD
GND
ISL6532BCR
0 to 70
0 to 70
20 Ld 6x6 QFN L20.6x6
ISL6532BCRZ
(See Note)
20 Ld 6x6 QFN L20.6x6
(Pb-free)
VTT
COMP
FB
VDDQ
*Add “-T” suffix to part number for tape and reel packaging.
6
7
8
9
10
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
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