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IS61WV102416FALL-20T2LI PDF预览

IS61WV102416FALL-20T2LI

更新时间: 2024-01-03 10:03:05
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
19页 711K
描述
Standard SRAM, 1MX16, 20ns, CMOS, PDSO54, TSOP2-54

IS61WV102416FALL-20T2LI 技术参数

生命周期:Active包装说明:TSOP2,
Reach Compliance Code:unknownHTS代码:8542.32.00.41
风险等级:5.66最长访问时间:20 ns
JESD-30 代码:R-PDSO-G54长度:22.22 mm
内存密度:16777216 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:54字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
座面最大高度:1.2 mm最大供电电压 (Vsup):2.2 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

IS61WV102416FALL-20T2LI 数据手册

 浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第2页浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第3页浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第4页浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第5页浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第6页浏览型号IS61WV102416FALL-20T2LI的Datasheet PDF文件第7页 
IS61WV102416FALL  
IS61/64WV102416FBLL  
PRELIMINARY INFORMATION  
DECEMBER 2016  
1Mx16 HIGH-SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY  
FEATURES  
The ISSI IS61/64WV102416FALL/BLL are high-speed, 16M  
bit static RAMs organized as 1024K words by 16 bits. It is  
fabricated using ISSI's high-performance CMOS technology.  
High-speed access time: 8ns, 10ns, 20ns  
High- performance, low power CMOS process  
Multiple center power and ground pins for  
greater noise immunity  
This highly reliable process coupled with innovative circuit  
design techniques, yields high-performance and low power  
consumption devices.  
TTL compatible inputs and outputs  
Single power supply  
1.65V-2.2V VDD (IS61WV102416FALL)  
2.4V-3.6V VDD (IS61/64WV102416FBLL)  
When CS# is HIGH (deselected), the device assumes a  
standby mode at which the power dissipation can be reduced  
down with CMOS input levels. Easy memory expansion is  
provided by using Chip Enable and Output Enable inputs.  
The active LOW Write Enable (WE#) controls both writing  
and reading of the memory.  
Packages available :  
- 48 ball mini BGA (6mm x 8mm)  
- 48 pin TSOP (Type I)  
- 54 pin TSOP (Type II)  
A data byte allows Upper Byte (UB#) and Lower Byte (LB#)  
access.  
Industrial and Automotive temperature support  
Lead-free available  
Data Control for upper and lower bytes  
The devices are packaged in the JEDEC standard 48-Pin  
TSOP (TYPE I), 48-pin mini BGA (6mm x 8mm), and 54-Pin  
TSOP (TYPE II) .  
DESCRIPTION  
FUNCTIONAL BLOCK DIAGRAM  
1024K x 16  
MEMORY  
ARRAY  
DECODER  
A0 A19  
VDD  
GND  
I/O  
I/O0 I/O7  
COLUMN I/O  
DATA  
CIRCUIT  
I/O8 I/O15  
CS# or  
CS1#/CS2  
CONTROL  
CIRCUIT  
OE#  
WE#  
UB#  
LB#  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
1
Rev. 0A  
12/13/2016  

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