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IS61S6432-133TQ PDF预览

IS61S6432-133TQ

更新时间： 2024-02-03 11:01:26
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
19页 141K
描述
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

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IS61S6432-133TQ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：unknown
风险等级：5.91最长访问时间：5 ns
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：32端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified最大待机电流：0.005 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.205 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUAD

IS61S6432-133TQ 数据手册

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®
IS61S6432  
64K x 32 SYNCHRONOUS  
PIPELINE STATIC RAM  
ISSI  
JUNE 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61S6432 is a high-speed, low-power  
synchronous static RAM designed to provide a burstable,  
high-performance, secondary cache for the Pentium™,  
680X0™, and PowerPC™ microprocessors. It is organized  
as 65,536 words by 32 bits, fabricated withISSI'sadvanced  
CMOS technology. The device integrates a 2-bit burst  
counter, high-speed SRAM core, and high-drive capability  
outputs into a single monolithic circuit. All synchronous  
inputs pass through registers controlled by a positive-edge-  
triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin TQFP and PQFP package  
• Single +3.3V power supply  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3  
controls DQ17-DQ24, BW4 controls DQ25-DQ32,  
conditionedbyBWEbeingLOW.ALOWonGWinputwould  
cause all bytes to be written.  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally by the IS61S6432 and controlled by the ADV  
(burst address advance) input pin.  
– ZZ in normal operation mode  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
• Industrial temperature available  
Asynchronous signals include output enable (OE), sleep  
modeinput(ZZ),clock(CLK)andburstmodeinput(MODE).  
A HIGH input on the ZZ pin puts the SRAM in the power-  
down state. When ZZ is pulled LOW (or no connect), the  
SRAM normally operates after three cycles of the wake-up  
period. A LOW input, i.e., GNDQ, on MODE pin selects  
LINEARBurst. AVCCQ (ornoconnect)onMODEpinselects  
INTERLEAVED Burst.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-200(1)  
-166  
5
-133  
5
-117  
5
-5  
5
-6  
6
-7  
7
-8  
8
Unit  
ns  
CLK Access Time  
Cycle Time  
4
5
tKC  
6
7.5  
133  
8.5  
117  
10  
100  
12  
83  
13  
75  
15  
66  
ns  
—
Frequency  
200  
166  
MHz  
Note:  
1. ADVANCE INFORMATION ONLY.  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. • 1-800-379-4774  
Rev. B  
1
06/28/01  
1234567...19

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