Datasheet > IS61LPS102418-250B2I

IS61LPS102418-250B2I

更新时间： 2024-11-12 05:23:51

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	166K
描述
Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61LPS102418-250B2I 数据手册

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第2页

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第3页

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第4页

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第5页

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第6页

浏览型号IS61LPS102418-250B2I的Datasheet PDF文件第7页

IS61VPS51236A IS61VPS102418A

IS61LPS51236A IS61LPS102418A

ISSI

512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

ADVANCE INFORMATION

DECEMBER 2002

DESCRIPTION

FEATURES

The ISSI IS61LPS/VPS51236A and IS61LPS/

VPS102418Aarehigh-speed,low-powersynchronousstatic

RAMsdesignedtoprovideburstable,high-performancememory

for communication and networking applications. The

IS61LPS/VPS51236Aisorganizedas524,288wordsby36

bits, and the IS61LPS/VPS102418A is organized as

1,048,576 words by 18 bits. Fabricated with ISSI's ad-

vanced CMOS technology, the device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). In addition, Global

Write (GW) is available for writing all bytes at one time,

regardless of the byte write controls.

LPS: V^DD3.3V + 5%, VDDQ 3.3V/2.5V + 5%

VPS: V^DD2.5V + 5%, VDDQ 2.5V + 5%

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

• JEDEC 100-Pin TQFP,

119-pin PBGA, and 165-pin PBGA package

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

250

2.6

200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

Integrated Silicon Solution, Inc. — 1-800-379-4774

ADVANCEINFORMATION Rev. 00A

12/17/02

12 3 4 5 6 7...29

中文翻译

下载PDF

与IS61LPS102418-250B2I相关器件

型号	品牌	获取价格	描述	数据表
IS61LPS102418-250B3	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61LPS102418-250B3I	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165
IS61LPS102418-250TQ	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS102418-250TQI	ISSI	获取价格	Cache SRAM, 1MX18, 2.6ns, CMOS, PQFP100, TQFP-100
IS61LPS102418A	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS102418A-200B2	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS102418A-200B2I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS102418A-200B3	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS102418A-200B3I	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC
IS61LPS102418A-200TQ	ISSI	获取价格	256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC

与IS61LPS102418-250B2I相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61LPS102418-250B2I

IS61LPS102418-250B2I 数据手册

与IS61LPS102418-250B2I相关器件

与IS61LPS102418-250B2I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61LPS102418-250B2I

IS61LPS102418-250B2I 数据手册

与IS61LPS102418-250B2I相关器件

与IS61LPS102418-250B2I相关文章

您还可以找

您在本页遇到什么问题？