Datasheet > IS49NLC93200-25EBL

IS49NLC93200-25EBL

更新时间： 2024-01-15 16:55:45

品牌	Logo	应用领域
美国芯成 - ISSI		时钟动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
35页	1254K
描述
DDR DRAM, 32MX9, 2.5ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144

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IS49NLC93200-25EBL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	TBGA, BGA144,12X18,40/32
针数：	144	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.28
风险等级：	5.7	访问模式：	MULTI BANK PAGE BURST
最长访问时间：	2.5 ns	其他特性：	AUTO REFRESH
最大时钟频率 (fCLK)：	400 MHz	I/O 类型：	COMMON
交错的突发长度：	2,4,8	JESD-30 代码：	R-PBGA-B144
长度：	18.5 mm	内存密度：	301989888 bit
内存集成电路类型：	DDR DRAM	内存宽度：	9
功能数量：	1	端口数量：	1
端子数量：	144	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA144,12X18,40/32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	电源：	1.5/1.8,1.8,2.5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	DRAMs	最大压摆率：	0.98 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	11 mm
Base Number Matches：	1

IS49NLC93200-25EBL 数据手册

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IS49NLC93200,IS49NLC18160,IS49NLC36800

Notes:

1) IDD specifications are tested after the device is properly initialized. +0°C ≤ T_C≤ +95°C; +1.7V ≤ V_DD≤ +1.9V, +2.38V ≤ V_EXT≤ +2.63V, +1.4V ≤ V_DDQ≤ V_DD, V_REF

V_DDQ/2.

2) t_CK= t_DK= MIN, t_RC= MIN.

3) Definitions for IDD conditions:

b. HIGH is defined as V_IN≥ V_IH(AC) MIN.

c. Stable is defined as inputs remaining at a HIGH or LOW level.

LOW is defined as V_IN≤ V_IL(AC) MAX.

d. Floating is defined as inputs at V_REF= V_DDQ/2.

e. Continuous data is defined as half the D or Q signals changing between HIGH and LOW every half clock cycle (twice per clock).

Continuous address is defined as half the address signals changing between HIGH and LOW every clock cycle (once per clock).

Sequential bank access is defined as the bank address incrementing by one every t_RC

h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every

other clock, and for BL = 8 this is every fourth clock.

4) CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.

5) IDD parameters are specified with ODT disabled.

6) Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications

and device operations are tested for the full voltage range specified.

7) IDD tests may use a V_IL-to-V_IHswing of up to 1.5V in the test environment, but input timing is still referenced to V_REF(or to the crossing point for CK/CK#).

Parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the

device is 2 V/ns in the range between V_IL(AC) and V_IH(AC).

2.5 Recommended AC Operating Conditions

(+0°C ≤ T_C≤ +95°C; +1.7V ≤ V_DD≤ +1.9V, unless otherwise noted.)

Parameter

Input HIGH voltage

Input LOW voltage

Symbol

V_IH(AC)

V_IL(AC)

Min

V_REF+ 0.2

Max

V_REF– 0.2

Units

Notes:

1. Overshoot: V_IH(AC) ≤ V_DDQ+ 0.7V for t ≤ t_CK/2.

2. Undershoot: V_IL(AC) ≥ – 0.5V for t ≤ t_CK/2.

3. Control input signals may not have pulse widths less than t_CKH(MIN) or operate at cycle rates less than t_CK(MIN.).

2.6 Temperature and Thermal Impedance

Temperature Limits

Min

Max

+110

+100

+95

Parameter

Symbol

Units

°C

Reliability junction temperature ¹

Operating junction temperature ²

Operating case temperature ³

T_J

T_C

°C

Notes:

1. Temperatures greater than 110°C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or above this

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability of the part.

2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow.

3. MAX operating case temperature; T_Cis measured in the center of the package. Device functionality is not guaranteed if the device exceeds maximum T_Cduring

operation.

Thermal Resistance

Theta-ja

(Airflow = 0m/s)

Theta-ja

(Airflow = 1m/s) (Airflow = 2m/s)

19.1 17.2

Theta-ja

Package

Substrate

4-layer

Unit

C/W

Theta-jc

2.4

144-ball FBGA

20.6

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. A1, 06/03/2016

1...5 6 789 10 11...35

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与IS49NLC93200-25EBL相关器件

型号	品牌	描述	获取价格	数据表
IS49NLC93200-25EBLI	ISSI	DDR DRAM, 32MX9, 2.5ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144	获取价格
IS49NLC93200-25EWBLI	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-25WBL	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-25WBLI	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-33B	ISSI	DDR DRAM, 32MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, FBGA-144	获取价格
IS49NLC93200-33BI	ISSI	DDR DRAM, 32MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, FBGA-144	获取价格

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