Datasheet > IS49NLC93200-25EBL

IS49NLC93200-25EBL

更新时间： 2024-02-21 00:46:26

品牌	Logo	应用领域
美国芯成 - ISSI		时钟动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
35页	1254K
描述
DDR DRAM, 32MX9, 2.5ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144

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IS49NLC93200-25EBL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	TBGA, BGA144,12X18,40/32
针数：	144	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.28
风险等级：	5.7	访问模式：	MULTI BANK PAGE BURST
最长访问时间：	2.5 ns	其他特性：	AUTO REFRESH
最大时钟频率 (fCLK)：	400 MHz	I/O 类型：	COMMON
交错的突发长度：	2,4,8	JESD-30 代码：	R-PBGA-B144
长度：	18.5 mm	内存密度：	301989888 bit
内存集成电路类型：	DDR DRAM	内存宽度：	9
功能数量：	1	端口数量：	1
端子数量：	144	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA144,12X18,40/32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	电源：	1.5/1.8,1.8,2.5 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	DRAMs	最大压摆率：	0.98 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	11 mm
Base Number Matches：	1

IS49NLC93200-25EBL 数据手册

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IS49NLC93200,IS49NLC18160,IS49NLC36800

1.4 Ball Descriptions

Symbol

Type

Description

Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE

CK.

Input

BA*

Input

Bank address inputs: Selects to which internal bank a command is being applied to.

Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising

edge of CK. CK# is ideally 180 degrees out of phase with CK.

CK, CK#

Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the

command decoder is disabled, new commands are ignored, but internal operations continue.

CS#

Input

I/O

Data input: The DQ signals form the data bus. During READ commands, the data is referenced to both

edges of QK*. During WRITE commands, the data is sampled at both edges of DK.

DQ*

Input data clock: DK* and DK*# are the differential input data clocks. All input data is referenced to

both edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17

are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18

devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the

device.

Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM

is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to

ground if not used.

DK*, DK*#

Input

TCK

TMS,TDI

Input

IEEE 1149.1 clock input: This ball must be tied to V_SSif the JTAG function is not used.

IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.

Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the

command to be executed.

Input reference voltage: Nominally V_DDQ/2. Provides a reference voltage for the input buffers.

External impedance (25–60Ω): This signal is used to tune the device outputs to the system data bus

impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.

Connecting ZQ to GND invokes the minimum impedance mode.

WE#, REF#

V_REF

Input

I/O

Output data clocks: QK* and QK*# are opposite polarity, output data clocks. They are free running, and

during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of

QK*, QK*#

Output phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are

aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and

QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.

QVLD

TDO

Output Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.

IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function is not

Output

used.

V_DD

V_DDQ

V_EXT

V_SS

Supply Power supply: Nominally, 1.8V.

Supply DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.

Supply Power supply: Nominally, 2.5V.

Supply Ground.

V_SSQ

V_TT

Supply DQ ground: Isolated on the device for improved noise immunity.

Supply Power supply: Isolated termination supply. Nominally, V_DDQ/2.

A21

A22

DNU

Reserved for future use: This signal is internally connected.

Reserved for future use: This signal is not connected and can be connected to ground.

Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.

No function: These balls can be connected to ground.

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. A1, 06/03/2016

1 2 3 456 7 8...35

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与IS49NLC93200-25EBL相关器件

型号	品牌	描述	获取价格	数据表
IS49NLC93200-25EBLI	ISSI	DDR DRAM, 32MX9, 2.5ns, CMOS, PBGA144, 11 X 18.50 MM, LEAD FREE, FBGA-144	获取价格
IS49NLC93200-25EWBLI	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-25WBL	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-25WBLI	ISSI	DDR DRAM, 32MX9, CMOS, PBGA144, WBGA-144	获取价格
IS49NLC93200-33B	ISSI	DDR DRAM, 32MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, FBGA-144	获取价格
IS49NLC93200-33BI	ISSI	DDR DRAM, 32MX9, 3.3ns, CMOS, PBGA144, 11 X 18.50 MM, FBGA-144	获取价格

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