IS42/45R86400D/16320D/32160D
IS42/45S86400D/16320D/32160D
16Mx32, 32Mx16, 64Mx8
512Mb SdRAM
PRELiMiNARY iNFORMATiON
JUNE 2011
PAcKAGE iNFORMATiON
FEATURES
iS42/45S32160d iS42/45S16320d iS42/45S86400d
•ꢀ Clockꢀfrequency:ꢀ200,ꢀ166,ꢀ143ꢀꢀMHz
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ
positiveꢀclockꢀedge
iS42/45R32160d iS42/45R16320d iS42/45R86400d
4Mꢀxꢀ32ꢀxꢀ4ꢀ
banks
8Mꢀxꢀ16ꢀxꢀ4ꢀꢀ
banks
16Mꢀxꢀ8ꢀxꢀ4ꢀꢀ
banks
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge
•ꢀ Powerꢀsupply:ꢀVdd/Vddq = 2.3V-3.6V
ꢀ IS42/45SxxxxxDꢀ-ꢀVdd/Vddq = 3.3Vꢀ
ꢀ IS42/45RxxxxxDꢀ-ꢀVdd/Vddq = 2.5ꢀꢀꢀ
•ꢀ LVTTLꢀinterface
•ꢀ Programmableꢀburstꢀlengthꢀꢀ
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)
•ꢀ Programmableꢀburstꢀsequence:ꢀꢀ
Sequential/Interleaveꢀ
90-ballꢀTF-BGA
54-pinꢀTSOP-II
54-ballꢀTF-BGA
54-pinꢀTSOP-II
KEY TiMiNG PARAMETERS
Parameter
ClkꢀCycleꢀTimeꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
-5
-6
-7
ꢀ
7ꢀ
7.5ꢀ
Unꢀt
ꢀ
nsꢀ
ns
ꢀꢀ
5ꢀ
10ꢀ
ꢀ
6ꢀ
10ꢀ
ClkꢀFrequencyꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀꢀ
200ꢀ
100ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ AutoꢀRefreshꢀ(CBR)
•ꢀ SelfꢀRefresh
167ꢀ
100ꢀ
143ꢀ
133ꢀ
Mhzꢀ
Mhz
AccessꢀTimeꢀꢀfromꢀClockꢀ
ꢀ CASꢀLatencyꢀ=ꢀ3ꢀ
ꢀ CASꢀLatencyꢀ=ꢀ2ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ 8Kꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)
5.0ꢀ
6ꢀ
5.4ꢀ
6ꢀ
5.4ꢀ
5.4ꢀ
nsꢀ
ns
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀꢀ
operationsꢀcapability
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ
command
AddRESS TABLE
Parameter
16M x 32
32M x 16
64M x 8
Configuration 4Mꢀxꢀ32ꢀxꢀ4ꢀ
8Mꢀxꢀ16ꢀxꢀ4ꢀꢀ 16Mꢀxꢀ8ꢀxꢀ4ꢀꢀ
banks
•ꢀ Packages:ꢀꢀ
banks
BankꢀAddressꢀ BA0,ꢀBA1
Pins
banks
x8/x16:ꢀ54-pinꢀTF-TSOP-II,ꢀ54-ballꢀTF-BGAꢀ(x16ꢀonly)
x32:ꢀ90-ballꢀTF-BGA
BA0,ꢀBA1
BA0,ꢀBA1
•ꢀ TemperatureꢀRange:ꢀ
Autoprechargeꢀ A10/AP
Pins
A10/AP
A10/AP
Commercialꢀ(0oCꢀtoꢀ+70oC)
Industrialꢀ(-40oCꢀtoꢀ+85oC)
Automotive,ꢀA1ꢀ(-40oCꢀtoꢀ+85oC)
RowꢀAddress 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12) 8K(A0ꢀ–ꢀA12)
Columnꢀ
512(A0ꢀ–ꢀA8) 1K(A0ꢀ–ꢀA9)
2K(A0ꢀ–ꢀA9,ꢀ
A11)
Automotive,ꢀA2ꢀ(-40oCꢀtoꢀ+105oC)
Address
RefreshꢀCountꢀ
ꢀ
ꢀ
ꢀ
Com./Ind./A1ꢀ 8Kꢀ/ꢀ64msꢀ
A2 8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64msꢀ
8Kꢀ/ꢀ16ms
8Kꢀ/ꢀ64msꢀ
8Kꢀ/ꢀ16ms
dEvicE OvERviEW
ISSI'sꢀ512MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ
dataꢀtransferꢀusingꢀpipelineꢀarchitecture.ꢀꢀAllꢀinputsꢀandꢀ
outputsꢀsignalsꢀreferꢀꢀtoꢀtheꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀ
Theꢀ512MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwith-
outꢀnotice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀ
theꢀlatestꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀ
reasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀap-
plicationsꢀunlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
Integrated Silicon Solution, Inc. — www.issi.comꢀ
1
Rev.ꢀ00B
06/09/2011
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