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INTEGRA

更新时间： 2024-11-15 23:58:39

品牌	Logo	应用领域
其他 - ETC		接收机
页数	文件大小	规格书
2页	32K
描述
Integra L64754 ISDB-S DVB/DSS Satellite Receiver

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Integr a L64754 ISDB-S

DVB/DSS Satellite Receiver

FEATURES

OVERVI EW

• O n-chip dua l differentia l 6-bit

A/ D converters

The L64754 is a sa tellite receiver demodula tor designed specifica lly to

meet the needs of Ja pa nese sa tellite broa dca st digita l TV. Providing ma ximum

integra tion a nd flexibility for system designers a t a minimum cost, the L64754

chip reduces the number of externa l components required to build a system.

LSI Logic fa brica tes the L64754 using its G12, 1.8 core/ 3.3 volt I/ O , 0. I 8-

micron, HCMO S process technology.

• Variable data rate of 1 to 45

Mbaud

• Seria l host interfa ce compa tible

with the LSI Logic seria l control

bus interfa ce

The L64754 demodula tor interfa ces with a ny tuner IC, which directly down-

converts satellite signal from L-band to baseband, and includes an on-chip synthesizer

controller. The L64754 generates control signals for a tuner IC synthesizer (using

frequency information programmed into the L64754 configuration registers), and

generates dual AGC control voltages for the two-stage automatic gain control on a

tuner IC chip.

• Correction for Q ua dra ture

pha se, a mplitude imba la nce

• Integrated PLL for clock synthesis

for use of funda menta l mode

crysta l

• Fa st cha nnel-switching mode

• Anti-a lia sing filters

The L64754 sa tellite demodula tor conta ins two ma in blocks: a

BPSK/ Q PSK/ 8PSK demodula tor a nd a conca tena ted FEC decoder.

• O n-chip digita l clock

synchroniza tion

The B/ Q / 8PSK demodula tor performs demodula tion for a ny of the three

modulation formats, a method of extracting a digital signal from a phase-modulated

a na log signa l. The B/ Q / 8PSK module is designed specifica lly for a sa tellite

broadcast digital TV receiver, and is compliant with the Japanese ISDB-S standard.

The demodula tor works a s per the Europea n digita l video broa dca st (DVB-S)

sta nda rd a nd the technica l specifica tions for DSS systems.

• Progra mma ble ma tched filter

• Synthesizer control-programmable

counters

• Power estima tion for AGC

control-dua l AGC outputs to

a llow two-sta ge AGC

To Tuner IC?

AGC

• O n-chip C/ N, BER estima tors

Control

B/Q/8PSK

Demodulator

Carrier

Loop Control

• Bit-error monitoring for cha nnel

performa nce mea surements for

a ll possible ISDB-S/ DVB/ DSS

ra tes

Timimg

Loop Control

Channel Imput

From Tuner IC

N/T "

DEMI

Matched

Filter

Output

Control

Linear

Eq.

Dual

ADC

1/T

Interpolator /Decimation Filter

• O n-chip block de-interlea ver

DEMQ

Clk (from L64754

onchip PLL)

• Power-down a nd Sta ndby

modes

Microcontroller Data and Address Bus

External Microcontroller Data and Address Bus

Synthesizer

Control

To Tuner IC

• O n-chip controller frees host

processor

Lowpass Filter

Control

Microcontroller Data and Address Bus

Block

Channel

Output

(MPEG-2)

Transport

Stream)

Reed Solomon

Decoder

Deinterleaver

and Frame Data

Descrambler

Pragmatic

TCM Decoder

Out, Interface

TMCC

Descrambler

FEC Decoder

Pipeline

TMCC Control

Th e

Integra™ L64754 Block Diagram

Co m m u n ica tio n s

Co m p a n y

中文翻译

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