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IMP811JEUS-T PDF预览

IMP811JEUS-T

更新时间: 2024-10-27 22:09:55
品牌 Logo 应用领域
IMP 微处理器监控
页数 文件大小 规格书
8页 139K
描述
4-pin レP Voltage Supervisor with Manual Reset

IMP811JEUS-T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:, TO-253LOWReach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.78可调阈值:NO
模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUITJESD-30 代码:R-PDSO-G4
JESD-609代码:e0端子数量:4
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装等效代码:TO-253LOW
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:1.2/5.5 V认证状态:Not Qualified
子类别:Power Management Circuits最大供电电流 (Isup):0.025 mA
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:DUAL
阈值电压标称:+4VBase Number Matches:1

IMP811JEUS-T 数据手册

 浏览型号IMP811JEUS-T的Datasheet PDF文件第2页浏览型号IMP811JEUS-T的Datasheet PDF文件第3页浏览型号IMP811JEUS-T的Datasheet PDF文件第4页浏览型号IMP811JEUS-T的Datasheet PDF文件第6页浏览型号IMP811JEUS-T的Datasheet PDF文件第7页浏览型号IMP811JEUS-T的Datasheet PDF文件第8页 
IMP811, IMP812  
Detailed Description  
Reset Timing and Manual Reset (MR)  
The reset signal is asserted–LOW for the IMP811 and HIGH for  
the IMP812 – when the VCC signal falls below the threshold trip  
voltage and remains asserted for 140ms minimum after the VCC  
has risen above the threshold.  
MR may be connected to a normally-open switch connected to  
ground without an external debounce circuit.  
For added noise rejection, a 0.1µF capacitor from MR to Ground  
can be added.  
A logic low on MR asserts RESET LOW on the IMP811 and HIGH  
on the IMP812. MR is internally pulled high through a 20kΩ  
resistor and can be driven by TTL/CMOS gates or with open  
collector/drain outputs. MR can be left open if not used.  
5V  
VCC  
VTH  
0V  
Active Reset  
Timeout Period  
140ms  
minimum  
5V  
MR  
Active Reset  
0V  
Timeout Period  
5V  
0V  
RESET  
RESET  
IMP811  
5V  
0V  
IMP812  
811/12_03.eps  
Figure 1. Reset Timing and Manual Reset (MR)  
©
1999 IMP, Inc.  
408-432-9100/www.impweb.com  
5

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