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IMISG742AYB

更新时间： 2024-02-15 17:02:22
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管
页数 文件大小 规格书
10页 429K
描述
Clock Generator, PDSO48,

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IMISG742AYB 技术参数

是否Rohs认证： 不符合生命周期：Active
Reach Compliance Code：compliant风险等级：5.88
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
电源：2.5,3.3 V认证状态：Not Qualified
子类别：Clock Generators最大压摆率：116 mA
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

IMISG742AYB 数据手册

 浏览型号IMISG742AYB的Datasheet PDF文件第1页浏览型号IMISG742AYB的Datasheet PDF文件第3页浏览型号IMISG742AYB的Datasheet PDF文件第4页浏览型号IMISG742AYB的Datasheet PDF文件第5页浏览型号IMISG742AYB的Datasheet PDF文件第6页浏览型号IMISG742AYB的Datasheet PDF文件第7页 
SG742  
Spread Spectrum Clock Generator for Pentium & Pentium II, 3 DIMM Designs  
Preliminary  
PIN DESCRIPTION  
PIN  
No.  
4
Pin  
Name  
Xin  
PWR  
VDD  
I/O  
I
TYPE  
Description  
OSC1  
On-chip reference oscillator input pin. Requires either an external  
crystal (nominally 14.318 MHz) or externally generated reference  
signal  
5
VDD  
O
OSC1  
BUF  
O-chip reference oscillator output p. Drives an external crystal  
When an externally generated reerence signal is used, is left  
unconnected  
This pin is bidirectional. If pin 5, MOE = 1 (default), then this  
pin is a REF1 buffered ouput of e crystal. If in 25, MODE = 0  
Xout  
46  
VDD  
-
O
I
REF1  
CS#  
PADI4 then this pin is CS# anis used in ower mnagement mode for  
PU  
synchronously stopnall CPU clock(e page 4).  
This pin is bidirectional. If s pulled low with a programming  
resistor at powrup then pin 7 is configured as an input pin which  
will act as a eference enable pfor pin 2 (this pin). If this pin is  
high (no ogramming resistor) at power up, then this pin is a  
REF1 bfered oput of the crystal.  
2
REF0  
SEL47  
CPU(0:3)  
IOAPIC  
44, 43, 41, 40  
47  
VDDC  
VDDI  
O
O
BUF1  
BUF2  
Clock outpsCPU freqncy table specified on page 1.  
IOAPIC clock r multprocessor support. Fixed frequency at  
14.31818 Mhz. is s a bidirectional pin. If Sel47 = 1, becomes  
APIC output powered by VDDq2. If Sel47 = 0, becomes input  
pin with internpull-up. When Refoff# = 1 (default), then REF0 is  
enabld, if efoff# is 0, then REF0 is disabled.  
I bus ocks. See frequency select table on page 1.  
Loskew (<250pS) PCI clock outputs. This pin is bidirectional.  
Ding power-up, It is an input ( TEST) and is used for configure  
te output frequency of CPU, SDRAM and PCI clocks into the  
TEST mode. When the power reaches the VDD rail (See Fig.1),  
the selected data is latched internally to the IC  
-
I
O
O
PAD  
BUF4  
BUF4  
REFOFF#  
PCICLK(3:4)  
PCI2  
12, 13  
11  
VDDP  
VDDP  
-
AD  
O
and this pins become PCI_F clock output.  
TEST  
PCI_F  
7
VDDP  
BUF4  
BUF4  
Low skew (<250pS) PCI clock outputs. This pin is bidirectional.  
During power-up, It is an input ( S1) and is used for HARD  
selecting the output frequency of CPU, SDRAM and PCI clocks,  
see Frequency table page1. When the power reaches the VDD  
rail (See Fig.1), the selected data is latched internally to the IC  
and this pins become PCI_F clock output.  
Low skew (<250pS) PCI clock outputs. This pin is bidirectional.  
During power-up, It is an input ( SW) and is used for HARD  
selecting the spreading width of the EMI reducing modulation.  
When the power reaches the VDD rail (See Fig.1), the data bit is  
latched internally in the IC and this pin becomes PCI1 clock  
output.  
-
I
O
S1  
PCI1  
10  
VP  
-
-
I
1
PAD  
PAD  
SW  
sden [0:1]  
23,24  
SDRAM clock enable pins. When these pins are brought to a  
Loigc 0 (low) level, they tri-state the SDRAM buffers they control.  
SDEN0 Controls SDRAM 4:7, SDEN1 controls SDRAM 8:11.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
Rev.1.3  
1/12/98  
Page 2 of 10  
1234567...10

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