Datasheet > IM8R-67025V-30

IM8R-67025V-30

更新时间： 2024-02-28 06:27:15

品牌	Logo	应用领域
TEMIC		静态存储器内存集成电路
页数	文件大小	规格书
23页	257K
描述
Dual-Port SRAM, 8KX16, 30ns, CMOS, CPGA84, PGA-84

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技术参数
数据手册

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IM8R-67025V-30 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	PGA-84	Reach Compliance Code：	unknown
风险等级：	5.88	最长访问时间：	30 ns
I/O 类型：	COMMON	JESD-30 代码：	S-CPGA-P84
JESD-609代码：	e0	内存密度：	131072 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	16
功能数量：	1	端口数量：	2
端子数量：	84	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX16	输出特性：	3-STATE
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	PGA
封装等效代码：	PGA84M,11X11	封装形状：	SQUARE
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	5 V	认证状态：	Not Qualified
最大待机电流：	0.0002 A	最小待机电流：	2 V
子类别：	SRAMs	最大压摆率：	0.32 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	PIN/PEG
端子节距：	2.54 mm	端子位置：	PERPENDICULAR
Base Number Matches：	1

IM8R-67025V-30 数据手册

M 67025

MATRA MHS

The dual-port RAM has a fast access time, and the two reading it. If the latch has been set the processor assumes

ports are completely independent of each another. This control over the shared resource. If the latch has not been

means that the activity on the left port cannot slow the set, the left processor has established that the right

access time of the right port. The ports are identical in processor had set the latch first, has the token and is using

function to standard CMOS static RAMs and can be read the shared resource. The left processor may then either

from, or written to, at the same time with the only possible repeatedly query the status of the semaphore, or abandon

conflict arising from simultaneous writing to, or a its request for the token and perform another operation

simultaneous READ/WRITE operation on,

whilst occasionally attempting to gain control of the

non-semaphore location. Semaphores are protected token through a set and test operation. Once the right side

against such ambiguous situations and may be used by the has relinquished the token the left side will be able to take

system program to prevent conflicts in the control of the shared resource.

non-semaphore segment of the dual-port RAM. The

devices have an automatic power-down feature

by writing a zero to a semaphore latch, and is relinquished

controlled by CS, the dual-port RAM select and SEM, the

again when the same side writes a one to the latch.

The semaphore flags are active low. A token is requested

semaphore enable. The CS and SEM pins control

The eight semaphore flags are located in a separate

on-chip-power-down circuitry that permits the port

memory space from the dual-port RAM in the M 67025.

concerned to go into stand-by mode when not selected.

The address space is accessed by placing a low input on

This conditions is shown in table 1 where CS and SEM

the SEM pin (which acts as a chip select for the

are both high.

semaphore flags) and using the other control pins

Systems best able to exploit the M 67025 are based

around multiple processors or controllers and are

typically very high-speed, software controlled or

software-intensive systems. These systems can benefit

from the performance enhancement offered by the

M 67025 hardware semaphores, which provide a lock-out

mechanism without the need for complex programming.

(address, OE and R/W) as normally used in accessing a

standard static RAM. Each of the flags has a unique

address accessed by either side through address pins

A0-A2. None of the other address pins has any effect

when accessing the semaphores. Only data pin D is used

when writing to a semaphore. If a low level is written to

an unused semaphore location, the flag will be set to zero

on that side and to one on the other side (see table 5). The

semaphore can now only be modified by the side showing

the zero. Once a one is writen to this location from the

same side, the flag will be set to one for both sides (unless

a request is pending from the other side) and the

semaphore can then be written to by either side.

Software handshaking between processors offers the

maximum level of system flexibility by permitting shared

resources to be allocated in varying configurations. The

M 67025 does not use its semaphore flags to control any

resources through hardware, thus allowing the system

designer total flexibility in system architecture.

The effect the side writing a zero to a semaphore location

has of locking out the other side is the reason for the use

of semaphore logic in interprocessor communication. (A

thorough discussion of the use of this feature follows

below). A zero written to the semaphore location from the

locked-out side will be stored in the semaphore request

latch for that side until the semaphore is relinquished by

the side having control. When a semaphore flag is read its

An advantage of using semaphores rather than the more

usual methods of hardware arbitration is that neither

processor ever incurs wait states. This can prove to be a

considerable advantage in very high speed systems.

How The Semaphore Flags Work

The semaphore logic is a set of eight latches independent value is distributed to all data bits so that a flag set at one

of the dual-port RAM. These latches can be used to pass reads as one in all data bits and a flag set at zero reads as

a flag or token, from one port to the other to indicate that all zeros. The read value is latched into the output register

a shared resource is in use. The semaphore provide the of one side when its semaphore select (SEM) and output

hardware context for the “Token Passing Allocation” enable (OE) signals go active. This prevents the

method of use assignment. This method uses the state of semaphore changing state in the middle of a read cycle as

a semaphore latch as a token indicating that a shared a result of a write issued by the other side. Because of this

resource is in use. If the left processor needs to use a latch, a repeated read of a semaphore flag in a test loop

resource, it requests the token by setting the latch. The must cause either signal (SEM or OE) to go inactive,

processor then verifies that the latch has been set by otherwise the output will never change.

Rev. D (29/09/95)

1...3 4 567 8 9...23

中文翻译

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与IM8R-67025V-30相关器件

型号	品牌	获取价格	描述	数据表
IM8R-67025V-35	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 35ns, CMOS, CPGA84, PGA-84
IM8R-67025V-55	TEMIC	获取价格	Dual-Port SRAM, 8KX16, 55ns, CMOS, CPGA84, PGA-84
IM-9	VISHAY	获取价格	Inductors
IM-910010%	VISHAY	获取价格	General Fixed Inductor, 1 ELEMENT, 68 uH, IRON-CORE, GENERAL PURPOSE INDUCTOR
IM-9120UH+-1%EWE2	VISHAY	获取价格	General Purpose Inductor, 120uH, 1%, Iron-Core,
IM-9120UH+-1%EZE2	VISHAY	获取价格	General Purpose Inductor, 120uH, 1%, Iron-Core,
IM-9120UH+-1%RB5	VISHAY	获取价格	General Purpose Inductor, 120uH, 1%, Iron-Core,
IM-9120UH+-10%EBE2	VISHAY	获取价格	General Purpose Inductor, 120uH, 10%, Iron-Core,
IM-9120UH+-10%ETE2	VISHAY	获取价格	General Purpose Inductor, 120uH, 10%, Iron-Core,
IM-9120UH+-10%EWE2	VISHAY	获取价格	General Purpose Inductor, 120uH, 10%, Iron-Core,

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