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IHLP5050CEER1R0M06 PDF预览

IHLP5050CEER1R0M06

更新时间: 2024-11-05 05:39:11
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
4页 136K
描述
10 % DCR Tolerance, Low Profile, Power Inductor

IHLP5050CEER1R0M06 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:5050
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8504.50.80.00风险等级:5.38
大小写代码:5050构造:Chip
型芯材料:COMPOSITE直流电阻:0.00321 Ω
标称电感 (L):1 µH电感器应用:POWER INDUCTOR
电感器类型:GENERAL PURPOSE INDUCTORJESD-609代码:e3
功能数量:1端子数量:2
最高工作温度:125 °C最低工作温度:-55 °C
封装高度:3.5 mm封装长度:13.2 mm
封装形式:SMT封装宽度:12.9 mm
包装方法:TR, 13 Inch最大额定电流:24 A
系列:IHLP-5050CE-06形状/尺寸说明:RECTANGULAR PACKAGE
屏蔽:YES特殊特征:DCR IS MEASURED AT 10% TOLERANCE
表面贴装:YES端子面层:Tin (Sn) - with Nickel (Ni) barrier
端子位置:DUAL ENDED端子形状:WRAPAROUND
测试频率:0.1 MHz容差:20%

IHLP5050CEER1R0M06 数据手册

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IHLP-5050CE-06  
Vishay Dale  
10 % DCR Tolerance,  
Low Profile, Power Inductor  
FEATURES  
Lowest height (3.5 mm) in this package footprint  
Shielded construction  
Frequency range up to 5.0 MHz  
Lowest DCR/µH, in this package size  
RoHS  
Handles high transient current spikes without saturation  
COM PLIANT  
Ultra low buzz noise, due to composite construction  
100 % lead (Pb)-free and RoHS compliant  
APPLICATIONS  
Tolerance DCR for current sense applications  
Improved current balance in phased power supplies  
Improved thermal management  
Manufactured under one or more of the following:  
US Patents; 6,198,375/6,204,744/6,449,829/6,460,244.  
Several foreign patents, and other patents pending.  
PDA/Notebook/Desktop/Server and Battery powered devices  
High current, Low profile POL converters  
DC/DC converters in distributed power systems  
DC/DC converter for Field Programmable Gate Arrays (FPGA)  
STANDARD ELECTRICAL SPECIFICATIONS  
DIMENSIONS in inches [millimeters]  
Lo  
HEAT RATING SATURATION  
Typical Pad Layout  
INDUCTANCE  
µH 20 % at  
DCRmΩ  
CURRENT  
DC AMPS3  
TYPICAL  
CURRENT  
DC AMPS4  
TYPICAL  
0.508  
[12.9ꢀ  
Max.  
0.542  
[13.76ꢀ  
10 %  
100 kHz, 0.25 V, 0 A at 25 °C  
0.195  
[4.95ꢀ  
0.60  
1.85  
29  
51  
0.310  
[7.87ꢀ  
0.138  
[3.5ꢀ Max.  
0.68  
1.0  
2.34  
3.21  
28  
24  
49  
40  
0.091 0.01  
[2.3 0.3ꢀ  
0.185 0.01  
1.5  
2.2  
3.3  
4.7  
5.6  
10  
4.97  
7.20  
19  
16  
12  
10  
9.5  
7
35  
29  
27  
24  
19  
14  
[4.7 0.3ꢀ  
0.520 0.015  
[13.2 0.38ꢀ Max.  
10.69  
14.27  
18.19  
30.86  
The diagram above applies to values 0.6 µH and below.  
Typical Pad Layout  
0.542  
[13.8ꢀ  
0.508  
[12.9ꢀ  
Max.  
NOTES:  
0.128 [3.3ꢀ  
1. All test data is referenced to 25 °C ambient  
2. Operating Temperature Range - 55 °C to + 125 °C  
0.318  
[8.1ꢀ  
0.138  
[3.5ꢀ Max.  
0.087 0.01  
3. DC current (A) that will cause an approximate ΔT of 40 °C  
4. DC current (A) that will cause Lo to drop approximately 20 %  
5. The part temperature (ambient + temp rise) should not exceed  
125 °C under worst case operating conditions. Circuit design,  
component placement, PWB trace size and thickness, airflow  
and other cooling provisions all affect the part temperature. Part  
temperature should be verified in the end application.  
[2.2 0.254ꢀ  
0.118 0.01  
[3.0 0.3ꢀ  
0.520 0.015  
[13.2 0.38ꢀ  
The diagram above applies to values 0.68 µH and above.  
DESCRIPTION  
1.0 µH  
IHLP-5050CE-06  
20 %  
ER  
e3  
INDUCTANCE  
VALUE  
MODEL  
INDUCTANCE  
TOLERANCE  
PACKAGE  
CODE  
JEDEC LEAD (Pb)-FREE  
STANDARD  
GLOBAL PART NUMBER  
I
H
L
P
5
0
5
0
C
E
E
R
1
R
0
M
0
6
INDUCTANCE  
VALUE  
SERIES  
MODEL  
INDUCTANCE  
TOLERANCE  
SIZE  
PACKAGE  
CODE  
www.vishay.com  
54  
For technical questions, contact: magnetics@vishay.com  
Document Number: 34165  
Revision: 21-Mar-06  

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