MULTI-ISSUE
IDT RC5000
64-BIT MICROPROCESSOR
Integrate d Device Technology, Inc.
•
High-performance memory system
- Large primary caches integrated on-chip
- Secondary cache control interface on-chip
- High-frequency 64-bit bus interface runs up to
100MHz
- Aggregate bandwidth of on-chip caches, system
interface of 5GB/s
- High-performance write protocols for graphics and
data communications
FEATURES
•
Dual issue super-scalar execution core, executing at
high-frequency
- 250 MHz frequency
- Dual issue floating-point ALU operations with other
instruction classes
- Traditional 5-stage pipeline, minimizes load and
branch latencies
- Single cycle repeat rate for most floating point ALU
operations
• MIPS-IV 64-bit ISA for improved computation
- Compound floating-point operations for 3D graphics
and floating-point DSP
•
•
High level of performance for a variety of applications
- High-performance 64-bit integer unit achieves 330
dhrystone MIPS (dhrystone 2.1)
- Ultra high-performance floating-point accelerator,
directly implementing single- and double-precision
operations achieves 500mflops
- Extremely large on-chip primary caches
- On-chip secondary cache controller
- Conditional move operations
Compatible with a variety of operating systems
- Windows™ CE
- Numerous MIPS-compatible real-time operating sys-
tems
Uses input system clock, with processor pipeline
clock multiplied by a factor of 2-8
Large on-chip TLB
•
•
Large, efficient on-chip caches
•
•
- 32KB Instruction Cache, 32KB Data Cache
- 2-set associative in each cache
- Virtually indexed and physically tagged to minimize
cache flushes
Active power management, including use of WAIT
operation
- Write-back and write-through selectable on a per
page basis
- Critical word first cache miss processing
- Supports back-to-back loads and stores in any com-
bination at full pipeline rate
BLOCK DIAGRAM
Phase Lock Loop
Data Tag A
Instruction Set A
Instruction Select
Data Set A
Store Buffer
DTLB Physical
SysAD
Integer Instruction Register
FP Instruction Register
Address Buffer
Instruction Tag A
ITLB Physical
Write Buffer
Read Buffer
Data Set B
DBus
Instruction Set B
IntIBus
Instruction Tag B
FPIBus
Control
AuxTag
Joint TLB
Tag
Load Aligner
Floating Point Register File
Unpacker/Packer
Integer Register File
Integer/Address Adder
Coprocessor 0
Data TLB Virtual
DVA
System/Memory
Control
Floating Point
MAdd,Add,Sub, Cvt
Div, SqRt
Shifter/Store Aligner
IVA
PC Incrementer
Branch Adder
Logic Unit
ABus
Instruction TLB Virtual
Program Counter
Integer Multiply, Divide
The IDT logo is a registered trademark and ORION, R4600, R4640, R4650, R4700, R5000, RV5000, and RISController are trademarks of Integrated Device Technology, Inc. MIPS is a registered
trademark of MIPS Computer Systems, Inc.
June, 1998
COMMERCIAL TEMPERATURE RANGE
1998 Integrated Device Technology, Inc.
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