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IDTVP386PAG8 PDF预览

IDTVP386PAG8

更新时间: 2024-09-16 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 接口集成电路
页数 文件大小 规格书
12页 114K
描述
Line Receiver

IDTVP386PAG8 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N接口集成电路类型:LINE RECEIVER
Base Number Matches:1

IDTVP386PAG8 数据手册

 浏览型号IDTVP386PAG8的Datasheet PDF文件第2页浏览型号IDTVP386PAG8的Datasheet PDF文件第3页浏览型号IDTVP386PAG8的Datasheet PDF文件第4页浏览型号IDTVP386PAG8的Datasheet PDF文件第5页浏览型号IDTVP386PAG8的Datasheet PDF文件第6页浏览型号IDTVP386PAG8的Datasheet PDF文件第7页 
DATASHEET  
ADVANCE INFORMATION  
8/28-BIT LVDS RECEIVER FOR VIDEO  
IDTVP386  
General Description  
Features  
Wide clock frequency range from 20 MHz to 100 MHz  
The VP386 is an ideal LVDS receiver that converts 4-pair  
LVDS data streams into parallel 28 bits of CMOS/TTL data  
with bandwidth up to 2.8 Gbps throughput or 350 Mbytes  
per second.  
Pin compatible with the National DS90CF386, THine  
THC63LVDF84, TISN65LVDS94  
Converts 4-pair LVDS data streams into parallel 28 bits of  
CMOS/TTL data  
This chip is an ideal means to solve EMI and cable size  
problems associated with wide, high-speed TTL interfaces  
through very low-swing LVDS signals.  
Fully spread spectrum compatible  
LVDS voltage swing of 350 mV for low EMI  
On-chip PLL requires no external components  
Low-power CMOS design  
Falling edge clock triggered outputs  
Power-down control function  
Compatible with TIA/EIA-644 LVDS standards  
Packaged in a 56-pin TSSOP (Pb free available)  
Block Diagram  
8
RED  
RxIN0+  
RxIN0-  
8
GREEN  
8
BLUE  
RxIN1+  
RxIN1-  
RxIN2+  
RxIN2-  
RxIN3+  
RxIN3-  
LVDS to TTL  
De-serializer  
HSYNC  
VSYNC  
DATA ENABLE  
CONTROL  
RxCLKIN+  
RxCLKIN-  
RxCLKOUT  
PLL  
PWRDWN  
VP386  
8/28-BIT LVDS RECEIVER FOR VIDEO  
1
IDTVP386  
7129/3  

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