Datasheet > IDTV105ADAG

IDTV105ADAG

更新时间： 2024-11-09 12:02:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
19页	324K
描述
DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER

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中文翻译

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技术参数
数据手册

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IDTV105ADAG 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.79
Base Number Matches：	1

IDTV105ADAG 数据手册

DATASHEET

ADVANCE INFORMATION

DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER

CONFIDENTIAL

IDTV105A

General Description

Features

The V105A LVDS display interface transmitter is designed

to support pixel data transmission between a video

processing engine and a digital video display. The dual

channel LVDS output supports pixel rates up to 150 MHz,

enabling compatibility with 1080p and WUXGA display

resolutions.

• Dual 32+3-bit LVTTL input supports up to 150 MHz pixel

rate.

• Dual pixel, LVDS output supports 150 MHz pixel rate

(compatible with 1080p and WUXGA resolution)

• Internal PLL requires no external loop filter

• Selectable rising or falling clock edge for data alignment

• Compatible with Spread Spectrum clock source

Total 67-bit LVCMOS/LVTTL input is provided. The V105A

converts the 67 bit parallel input data into two 5-pair LVDS

(Low Voltage Differential Signaling) serial data outputs, in

odd/even pixel format. Input data can be clocked on the

rising or falling edge of the input clock (selectable). In video

applications the 35 data bits are normally divided into 10

bits for each R, G and B channel and 5 control bits (which

includes VSYNC, HSYNC and DE).

• Reduced LVDS output voltage swing mode (selectable)

to minimize EMI

• Single 3.3 V supply

• Low power consumption CMOS design

• Power down mode

• Available in 144 pin LQFP package (14x14mm body size)

Block Diagram

TXA1+

TXA1-

TXB1+

TA1[9:0]

TB1[9:0]

TXB1-

TC1[9:0]

Data

TXC1+

RES1[2:1]

Serializer

TXC1-

TTL Input

TXD1+

TXD1-

TXE1+

TXE1-

TA2[9:0]

Data latch,

TB2[9:0]

Bit Mapper,

TC2[9:0]

Demux

RES2[2:1]

TXD2+

TXD2-

TXE2+

HSYNC

VSYNC

TXE2-

Data

TXA2+

Serializer

TXA2-

TXB2+

TXB2-

TXC2+

TXC2-

CTRL

MAP

R/F

TEST

TCLK1+

TCLK1-

PLL and

Device Timing

CLKIN

TCLK2+

TCLK2-

DUAL-CHANNEL,TRIPLE 10-BIT LVDS TRANSMITTER

IDTV105A

7121/3

CONFIDENTIAL

12 3 4 5 6 7...19

中文翻译

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