IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
Table 2 - Time Slot Selection for Linear GCI
S1 = 0, S0= 0
IDT821064
S1 = 0, S0= 1
Monitor
Voice
Channel
Monitor
Voice
Channel
Channels
Time Slot
Time Slot
Time Slot
Time Slot
and C/I
and C/I
1
2
3
4
Time slot 0
Time slot 0
Time slot 1
Time slot 1
A
B
A
B
Time slot 2
Time slot 2
Time slot 3
Time slot 3
A
B
A
B
Time slot 2
Time slot 2
Time slot 3
Time slot 3
A
B
A
B
Timeslot4
Timeslot4
Timeslot5
Timeslot5
A
B
A
B
S1 = 1, S0= 0
S1 = 1, S0= 1
Monitor
and C/I
Voice
Channel
Monitor
and C/I
Voice
Channel
Time Slot
Time Slot
Time Slot
Time Slot
1
2
3
4
Time slot 4
Time slot 4
Time slot 5
Time slot 5
A
B
A
B
Time slot 6
Time slot 6
Time slot 7
Time slot 7
A
B
A
B
Time slot 6
Time slot 6
Time slot 7
Time slot 7
A
B
A
B
Time slot 0
Time slot 0
Time slot 1
Time slot 1
A
B
A
B
C/I CHANNEL
In both compressed GCI and linear GCI mode, the upstream and
MONITOR CHANNEL
The monitor channel is used to read and write the internal global/local
downstream C/I channel bytes are continuously carrying I/O information registers and coefficient/FSK RAM of the IDT821064, or to provide SLIC
every frame to and from the IDT821064. In this way, the upstream processor signaling. Using two monitor control bits (MR and MX) per direction,
can have an immediate access to SLIC output data present on IDT821064’s data is transferred between the upstream and downstream devices in a
programmable I/O port through downstream C/I channel, as well as to complete handshake procedure. The MR and MX bits are contained in
SLIC input data through upstream C/I channel. The IDT821064 transmits the C/I channel byte of the GCI frame. See Figure 3.
or receives the C/I channel data with the Most Significant Bit first.
The monitor channel transmission operates on a pseudo-
The MR and MX bits are used for handshaking during data exchanges asynchronous basis:
on the monitor channel.
- Data transfer (bits) on the bus is synchronized to FSC;
- Data flow (bytes) are asynchronously controlled by the handshake
procedure.
Upstream C/I Channel
The C/I Channel which includes six C/I channel bits, is transmitted
For example: Data is placed onto the DD Monitor Channel by the
upstream by the IDT821064 every frame. The bit definitions for the upstream Monitor Transmitter of the master device (DD MX bit is activated and set
C/I channel are shown below.
Upstream C/I Octet
to ‘0’). This data transfer will be repeated within each frame (125ms rate)
until it is acknowledged by the IDT821064 Monitor Receiver by setting
LSB the DU MR bit to ‘0’, which is checked by the Master Transmitter of the
MSB
b7
SI1(A) SI2(A) SB1(A) SI1(B) SI2(B) SB1(B)
master device. Thus, the data rate is not 8-kbytes/sec.
b6
b5
b4
b3
b2
b1
b0
MR
MX
Monitor Handshake
The logic state of input ports SI1 and SI2 for channel A and channel B, as
well as the bidirectional port SB1 for channel A and B if SB1 is programmed
The monitor channel works in 3 states:
I. Idle state: A pair of inactive (high) MR and MX bits during two or
as an input, are read and transmitted in the upstream C/I channel. When more consecutive frames shows an idle state on the monitor channel
SB2 and SB3 are programmed as inputs, their data are not available in and the End of Message (EOM);
upstream C/I channel and can be read by Global Command 9 and 10
only.
II. Sending state: MX bit is activated (low) by the Monitor Transmitter,
together with data-bytes (can be changed) on the monitor channel;
III. Acknowledging: MR bit is set to active (low) by the Monitor Receiver,
together with a data byte remaining in the monitor channel.
A start of transmission is initiated by a monitor transmitter by sending
out an active MX bit together with the first byte of data to be transmitted in
Downstream C/I Channel
The downstream C/I octet is defined as:
Downstream C/I Octet
MSB
LSB the monitor channel. This state remains until the addressed monitor
receiver acknowledges the receipt of data by sending out an active low
b7
/B
b6
b5
b4
b3
b2
b1
b0
MX
MR bit. The data transmission is repeated each 125ms frame (minimum
is one repetition). During this time the Monitor Transmitter keeps
evaluating the MR bit.
SO2
SO1
SB3
SB2
SB1
MR
A
where, A/B selects channel A or Channel B:
A/B = 0: Channel A is selected; A/B = 1: Channel B is selected.
The downstream C/I channel carries the SLIC output data bits of SO1 place when the transmitters MX and the receivers MR bit are in active
and SO2 for channel A or B, as well as SB1, SB2 and SB3 output bits if state.
Flow control, means in the form of transmission delay, can only take
SB1, SB2 and SB3 are programmed as outputs.
Since the receiver is able to receive the monitor data at least twice (in
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