Datasheet > IDT821064PQF

IDT821064PQF

更新时间： 2024-02-12 15:25:30

品牌	Logo	应用领域
艾迪悌 - IDT		解码器编解码器 PC
页数	文件大小	规格书
33页	494K
描述
QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

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技术参数
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IDT821064PQF 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	PLASTIC, QFP-64	针数：	64
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	压伸定律：	A/MU-LAW
滤波器：	YES	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e0	长度：	14 mm
功能数量：	1	端子数量：	64
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	认证状态：	Not Qualified
座面最大高度：	2.45 mm	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	PROGRAMMABLE CODEC
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	14 mm

IDT821064PQF 数据手册

IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

INDUSTRIAL TEMPERATURE RANGE

The Frame Sync (FSC) pulse identifies the beginning of the Transmit

and Receive frames and all GCI time slots are referenced to it. The Data

Clock (DCL) is either 2.048 MHz or 4.096MHz, the internal circuit of

IDT821064 monitors this input to determine which frequency is being

used. The internal timing will be adjusted according to the DCL frequency

so that DU and DD operate at 2M rate.

IDT821064 allows both compressed and linear data format coding/

decoding. VDS bit in Global Regiser 5 makes the selection of voice data

format.

FUNCTIONAL DESCRIPTION

The IDT821064 is a four-channel PCM CODEC with on-chip digital

filters. It provides the four-wire solution for the subscriber line circuitry in

digital switches. The IDT821064 converts analog voice signals to digital

PCM samples and digital PCM samples back to analog voice signals.

Digital filters are used to bandlimit the voice signals during conversion.

High performance oversampling Analog-to-Digital Converters (ADC) and

Digital-to-Analog Converters (DAC) in the IDT821064 provide the required

conversion accuracy. The associated decimation and interpolation filters

are realized with both dedicated hardware and Digital Signal Processor

(DSP). The DSP also handles all other necessary functions such as

PCM bandpass filtering, sample rate conversion and PCM companding.

See the Functional Block Diagram.

COMPRESSED GCI MODE

In GCI compressed mode, one GCI frame consists of 8 GCI time

slots, the Data Upstream Interface transmits four 8-bit bytes per GCI

time slot. They are:

- Two voice data bytes from the A-law or m-law compressor for two

different channel, for easy description, we name the two channels as

channel A and channel B. The compressed voice data bytes for channel

A and B are 8-bit wide;

In the transmit path, the analog voice signal input from VIN pin is

converted to PCM code by ADC, DSP and PCM companding circuits.

Band-limiting functions as specified in ITU-T are implemented by digital

filters. At last the fully processed signal is transferred to the GCI interface,

in a compressed or linear signal presentation.

In the receive path, the digital signal is received via the GCI interface.

Then it is expanded and sent to the DSP for interpolation and receive

channel filtering function. The filtered signal is then sent to an

oversampling DAC. The DAC output is post-filtered and then delivered

at VOUT pin by a power amplifier. The amplifier can drive resistive load

higher than 300 W AC.

- One Monitor channel byte, which is used for reading control data

from the device for Channel A and B;

- One C/I channel byte, which contains a 6 bit width C/I channel sub-

byte together with an MX bit and an MR bit. All real time signaling infor-

mation is carried on the C/I channel sub-byte. The MX (Monitor Trans-

mit) bit and MR (Monitor Receive) bit are used for handshaking func-

tions for Channel A and B. Both MX and MR are active low.

Transmit logic controls the transmission of data onto the GCI bus.

The data structure of the Data Downstream is as same as that of

Upstream. The Data Downstream Interface logic controls the reception

of data bytes from the GCI bus. The two compressed voice channel

data bytes of the GCI time slot are transferred to the A-law or m-law ex-

pansion logic circuit. The expanded data is passed to the receive pathof

the signal processor. The Monitor Channel and C/I Channel bytes are trans-

ferred to the GCI control logic for processing.

GCI INTERFACE

The General Control Interface (GCI) provides communication of both

control and voice data between the GCI highway and SLIC over a pair of

pins on the IDT821064. The IDT821064 sends Data Upstream out of

the DU pin and receives Data Downstream on the DD pin. DCL and FS

are two input clock signals providing Data Clock (DCL) and Frame

Synchronization (FS) information for the device. A complete GCI frame

is sent upstream on DU pin and received downstream on DD pin every

125 ms.

Figure 1 shows the overall compressed GCI frame structure.

125 ms

FSC

DCL

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

Detail

TS3

Detail

M M

Voice Channel A

Voice Channel B

Monitor Channel C/I Channel

M M

Figure 1. Compressed GCI Frame Structure

1 2 345 6 7...33

中文翻译

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