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IDT821064PQF PDF预览

IDT821064PQF

更新时间： 2024-02-19 11:22:25
品牌 Logo 应用领域
艾迪悌 - IDT 解码器编解码器PC
页数 文件大小 规格书
33页 494K
描述
QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE

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IDT821064PQF 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：PLASTIC, QFP-64针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84压伸定律：A/MU-LAW
滤波器：YESJESD-30 代码：S-PQFP-G64
JESD-609代码：e0长度：14 mm
功能数量：1端子数量：64
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK认证状态：Not Qualified
座面最大高度：2.45 mm标称供电电压：5 V
表面贴装：YES电信集成电路类型：PROGRAMMABLE CODEC
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD宽度：14 mm

IDT821064PQF 数据手册

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INDUSTRIAL TEMPERATURE RANGE  
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE  
PIN DESCRIPTION  
Name  
Type  
Pin Number  
Description  
GNDA1  
GNDA2  
GNDA3  
GNDA4  
50  
54  
59  
63  
Analog Ground.  
All ground pins should be connected together.  
P
Digital Ground.  
All digital signals are referred to this pin.  
GNDD  
P
21  
+5V Analog Power Supply.  
These pins should be connected to ground via a 0.1 F capacitor. All power supply pins should be connected  
together.  
+5V Digital Power Supply.  
+5V Analog Power Supply.  
This pin should be connected to ground via a 0.1 F capacitor. All power supply pins should be connected  
together.  
Capacitor Noise Filter  
VDDA12  
VDDA34  
52  
61  
m
P
P
P
VDDD  
VDDB  
24  
57  
56  
m
CNF  
-
I
m
This pin should be connected to ground via a 0.22 F capacitor.  
Analog Voice Inputs.  
These pins should be connected to the SLIC via a capacitor (0.22 F).  
VIN1-4  
49, 55, 58, 64  
m
Voice Frequency Receiver Outputs.  
VOUT1-4  
SI1_(1-4)  
O
51, 53, 60, 62  
36, 47, 2, 13  
W
These pins can drive 300 AC load. They can drive transformers directly.  
I
SLIC signalling Inputs with debounced function for Channel 1-4.  
Bi-directional SLIC Signalling I/Os for Channel 1-4, can be programmed as Input or Output.  
SLIC Signalling Outputs for Channel 1-4.  
SI2_(1-4)  
SB1_(1-4)  
35, 48, 1, 14  
39, 44, 5, 10  
SB2_(1-4)  
I/O  
O
38, 45, 4, 11  
SB3_(1-4)  
SO1_(1-4)  
37, 46, 3, 12  
41, 42, 7, 8  
SO2_(1-4)  
DU  
40, 43, 6, 9  
26  
GCI Data Upstream  
GCI data is serially transmitted to this pin for all 4 channels of IDT821064.  
GCI Data Downstream  
GCI data is received serially from this pin for all 4 channels of IDT821064.  
O
I
DD  
FSC  
DCL  
27  
31  
32  
Frame Sync.  
I
FSC is an 8 kHz signal that identifies the beginning of Timeslot 0 in the GCI frame.  
Data Clock.  
The data clock is either 2.048 MHz or 4.096 MHz, which is determined automatically by IDT821064.  
I
S0  
S1  
18  
19  
Time Slot Select  
I
These pins are used to select one of the four time slot positions for Voice channels, Monitor and C/I channels.  
Master Clock Input.  
MCLK  
I
22  
Master clock provides the clock for DSP. It can be 2.048 MHz or 4.096 MHz, which is determined automatically by  
IDT821064. It is recommended to connect MCLK pin and DCL pin together.  
Reset Input.  
Forces the device to default state. Active low.  
Chopper Clock Output.  
Provides a programmable (2 -28 ms) output signal synchronous to MCLK.  
Chopper Clock Output.  
Provides a programmable 256 kHz, or 512 kHz or 16.384 MHz output signal synchronous to MCLK  
Recommend to be connected to GNDD.  
RESET  
I
23  
33  
16  
CHCLK1  
O
O
CHCLK2  
NCR  
17,30  
15,20,25  
28,29,34  
No connection  
NC  
3
1234567...33

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