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IDT79RC32V364-133DAI PDF预览

IDT79RC32V364-133DAI

更新时间： 2024-02-26 15:10:16
品牌 Logo 应用领域
其他 - ETC 外围集成电路微处理器时钟
页数 文件大小 规格书
21页 483K
描述
32-Bit Microprocessor

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IDT79RC32V364-133DAI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP144,.87SQ,20针数：144
Reach Compliance Code：not_compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.47
Is Samacsys：N地址总线宽度：32
位大小：32边界扫描：YES
最大时钟频率：67 MHz外部数据总线宽度：32
格式：FIXED POINT集成缓存：YES
JESD-30 代码：S-PQFP-G144JESD-609代码：e0
长度：20 mm低功率模式：YES
湿度敏感等级：3端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm速度：133 MHz
子类别：Microprocessors最大压摆率：360 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：20 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR, RISCBase Number Matches：1

IDT79RC32V364-133DAI 数据手册

 浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第5页浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第6页浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第7页浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第9页浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第10页浏览型号IDT79RC32V364-133DAI的Datasheet PDF文件第11页 
79RC32364™  
Pin  
Type  
Description  
Retry*  
I
Retry  
Indicates that the current bus cycle must be terminated. Retry* is ignored after acceptance of the first data during a read cycle. Dur-  
ing a write, Retry* is recognized in all data cycles.  
Initialization Interface  
ColdReset*  
I
ColdReset  
This active-low signal is used for power-on reset.  
Reset*  
I
Reset  
This active-low signal is used for both power-on and warm reset.  
DMA Interface  
BusReq*  
I
Bus Request  
This active-low signal is an input to the processor that is used to request mastership of the external interface bus. Mastership is  
granted according to the assertion of this input, taken back based on its negation.  
BusGnt*  
I/O  
Bus Grant/ModeBit(5)  
This active-low signal is an output from the processor and is used to indicate that the CPU has relinquished mastership of the exter-  
nal interface bus. BusGnt* goes low initially for at least 2 clocks to indicate that the CPU has relinquished mastership of the external  
interface bus. After going low, BusGnt* returns high, either when the CPU makes an internal request for the bus or after BusReq* is  
de-asserted.During the power-on reset (Cold Reset), BusGnt* is an input, ModeBit(5).  
Interrupt Interface  
NMI*  
I
Non-Maskable Interrupt  
NMI is falling edge sensitive and an asynchronous signal.  
Int*(5:0)  
I
Interrupt/ModeBit(9:6)  
These interrupt inputs are active low to the CPU. During power-on, Int*(3:0) serves as ModeBit(9:6).  
Debug Emulator Interface  
TCK  
I
Testclock  
An input test clock, used to shift into or out of the Boundary-Scan register cells. TCK is independent of the system and the processor  
clock with nominal 50% duty cycle.  
TDI/DINT*  
I
TDI/DINT*  
On the rising edge of TCK, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller  
state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit  
back to Run Time Mode (standard JTAG). Requires an external pull-up on the board.  
TDO/TPC  
O
TDO/TPC  
The TDO is serial data shifted out from instruction or data register on the falling edge of TCK. When no data is shifted out, the TDO  
is tri-stated. During Real Time Mode, this signal provides a non-sequential program counter at the processor clock or at a division of  
processor clock.  
TMS  
I
TMS  
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising  
edge of the TCK. Requires an external pull-up on the board.  
TRST*  
DCLK  
I
TRST*  
The TRST* pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. Requires an  
external pull-down on the board.  
O
DCLK  
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the TDO signal at the processor clock  
speed or any division of the internal pipeline.  
Table 3 System Interface Pin Descriptions (Page 3 of 4)  
8 of 21  
June 20, 2000  
*Notice: The information in this document is subject to change without notice  
1...567891011...21

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