IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
simple handshake signals to process CPU read and write to a given application, the system design engineer could
requests. Inadditiontothereadandwriteinterface, theR3051 include true burst support from the DRAM to provide for high-
family incorporates a DMA arbiter, to allow an external master performance cache miss processing, or utilize a simpler,
to control the external bus.
lowerperformancememorysystemtoreducecostandsimplify
TheR3081alsosupportshardwarebasedcachecoherency the design. Similarly, the system designer could choose to
during DMA writes. The R3081 can invalidate a specified line implement techniques such as external secondary cache, or
of data cache, or in fact can perform burst invalidations during DMA, to further improve system performance.
burst DMA writes.
The R3081 incorporates a 4-deep write buffer to decouple
DEVELOPMENT SUPPORT
the speed of the execution engine from the speed of the
memorysystem. ThewritebufferscaptureandFIFOprocessor
address and data information in store operations, and present
it to the bus interface as write transactions at the rate the
memory system can accommodate.
The R3081 read interface performs both single datum
reads and quad word reads. Single reads work with a simple
handshake, and quad word reads can either utilize the simple
handshake (in lower performance, simple systems) or utilize
atightertimingmodewhenthememorysystemcanburstdata
at the processor clock rate. Thus, the system designer can
choose to utilize page or nibble mode DRAMs (and possibly
use interleaving, if desired, in high-performance systems), or
use simpler techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3081 incorporates a 4-deep read buffer FIFO, so that the
external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
TheR3081isR3051supersetcompatibleinitsbusinterface.
Specifically, the R3081 has additional support to simplify the
design of very high frequency systems. This support includes
the ability to run the bus interface at one-half the processor
execution rate, as well as the ability to slow the transitions
between reads and writes to provide extra buffer disable time
for the memory interface. However, it is still possible to design
a system which, with no modification to the PC Board or
software, canaccepteitheranR3041, R3051, R3052, R3071,
or R3081.
The IDT R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications
software and utility libraries, logic analysis tools, sub-system
modules, and shrink wrap operating systems. The R3081,
which is pin and software compatible with the R3051, can
directly utilize these existing tools to reduce time to market.
Figure7isanoverviewofthesystemdevelopmentprocess
typically used when developing R3051 family applications.
The R3051 family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for R3051 family applications, and
include tools such as:
• OptimizingcompilersfromMIPS,theacknowledgedleader
in optimizing compiler technology.
• Cross development tools, available in a variety of
development environments.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT PROM Monitor.
• IDT/sim , which implements a full prom monitor
(diagnostics, remote debug support, peek/poke, etc.).
• IDT/kit , which implements a run-time support package for
R3051 family systems.
PERFORMANCE OVERVIEW
TheR3081achievesaveryhigh-levelofperformance. This
performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the execution engine
achieves over 35 VUPS performance when operating out
of cache.
• Afullfeaturedfloatingpointaccelerator/co-processor.
The R3081 incorporates an R3010A compatible floating
pointacceleratoron-chip,withindependentALUsforfloating
point add, multiply, and divide. The floating point unit is fully
hardware interlocked, and features overlapped operation
and precise exceptions. The FPA allows floating point
adds, multiplies, and divides to occur concurrently with
each other, as well as concurrently with integer operations.
• Largeon-chipcaches.TheR3051familycontainscaches
which are substantially larger than those on the majority of
today’smicroprocessors. Theselargecachesminimizethe
number of bus transactions required, and allow the R3051
family to achieve actual sustained performance very close
to its peak execution rate. The R3081 doubles the cache
available on the R3052, making it a suitable engine for
SYSTEM USAGE
The IDT R3051 family has been specifically designed to
allow a wide variety of memory systems. Low-cost systems
can use slow speed memories and simple controllers, while
otherdesignersmaychoosetoincorporatehigherfrequencies,
faster memories, and techniques such as DMA to achieve
maximum performance. The R3081 includes specific support
for high perfromance systems, including signals necessary to
implement external secondary caches, and the ability to
perform hardware based cache coherency in multi-master
systems.
Figure 6 shows a typical system implementation.
Transparent latches are used to de-multiplex the R3081
address and data busses from the A/D bus. The data paths
between the memory system elements and the A/D bus is
managed by simple octal devices. A small set of simple PALs
is used to control the various data path elements, and to
control the handshake between the memory devices and the
CPU.
Dependingonthecostvs.performancetradeoffsappropriate
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