IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
a double frequency clock. The 2x clock mode is provided for theperformanceinherentintheR3081. Aswiththeinstruction
compatiblitywiththeR3051.Theclockgeneratorunitreplaces cache, the data cache is implemented as a direct mapped
theexternaldelaylinerequiredinR3000A basedapplications. physicaladdresscache. Thecacheiscapableofmappingany
word within the 4GB physical address space.
Instruction Cache
The data cache is implemented as a write-through cache,
The R3081 implements a 16kB Instruction Cache. The to insure that main memory is always consistent with the
system may choose to repartition the on-chip caches, so that internal cache. In order to minimize processor stalls due to
the instruction cache is reduced to 8kB but the data cache is data write operations, the bus interface unit incorporates a 4-
increased to 8kB. The instruction cache is organized with a deep write buffer which captures address and data at the
line size of 16bytes (four entries). This large cache achieves processor execution rate, allowing it to be retired to main
hitratesinexcessof98%inmostapplications,andsubstantially memory at a much slower rate without impacting system
contributes to the performance inherent in the R3081. The performance. Further, support has been provided to allow
cache is implemented as a direct mapped cache, and is hardware based data cache coherency in a multi-master
capableofcachinginstructionsfromanywherewithinthe4GB environment, such as one utilizing DMA from I/O to memory.
physical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and thus fields.Parityisgeneratedbythereadbufferduringcacherefill;
does not require flushing on context switch. duringcachereferences,theparityischecked,andinthecase
The data cache is parity protected over the data and tag
Theinstructioncacheisparityprotectedovertheinstruction of a parity error, a cache miss is processed.
word and tag fields. Parity is generated by the read buffer
during cache refill; during cache references, the parity is Bus Interface Unit
checked, and in the case of a parity error, a cache miss is
processed.
The R3081 uses its large internal caches to provide the
majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slower memory devices. Alternately, a high-performance,
Data Cache
The R3081 incorporates an on-chip data cache of 4kB, low-cost secondary cache can be implemented, allowing the
organized as a line size of 4 bytes (one word). The R3081 processor to increase performance in systems where bus
allows the system to reconfigure the on-chip cache from the bandwidth is a performance limitation.
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and
8kB of Data caches.
AspartoftheR3051family,theR3081businterfaceutilizes
a 32-bit address and data bus multiplexed onto a single set of
The relatively large data cache achieves hit rates in excess pins. The bus interface unit also provides an ALE (Address
of 95% in most applications, and contributes substantially to Latch Enable) output signal to de-multiplex the A/D bus, and
Cache
Data Bus
Data
(32)
(32)
Instructions
Operands
Register Unit (16 X 64)
Exponent Part
Fraction
Condition
Codes
(11)
(11)
(11)
(53)
(53)
(53)
A
B
Result
A
B
Result
Add Unit
Exponent
Unit
Round
Control Unit
and Clocks
(53)
(53)
(53)
(56)
A
A
B
B
Result
Divide Unit
(53)
(56)
Result
Multiply Unit
2889 drw 05
Figure 5. FPA Functional Block Diagram
5.5
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