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IDT77V7111TF PDF预览

IDT77V7111TF

更新时间: 2024-11-11 19:56:39
品牌 Logo 应用领域
艾迪悌 - IDT 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
12页 216K
描述
Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64, 10 X 10 MM, TQFP-64

IDT77V7111TF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP64,.47SQ,20
针数:64Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.92
数据速率:1250000 MbpsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:10 mm
湿度敏感等级:3功能数量:1
端子数量:64收发器数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Network Interfaces标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

IDT77V7111TF 数据手册

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DATASHEET  
IDT77V7101  
GIGABIT ETHERNET  
SERDES TRANSCEIVER  
Features  
Applications  
IEEE802.3zGigabitEthernetcompatible  
IEEE802.3zGigabitmedia interfaces:  
1.25 Gbps full duplex transmission and reception in a single IC  
Opticalinterface throughfibermodule  
10-bit parallel TX and RX interfaces based on EIA/TIA X3T11  
SignalDetect,internalorexternal  
Code GroupRealignmentwithDisable  
InternalLoopbackmode  
62.5MHz recovered clock  
Low power 3.3V CMOS  
– 1000BASE-LXOptical  
· – 1000BASE-SX Optical  
Provides the PMAfunctionofthe PHY  
Highspeedcustomserialinterface  
Backplane seriallink  
Bus extension  
Description  
Fewexternalcomponents required  
64-pin10mmand14mmpackages  
TheIDT77V7101is amonolithic1.25Gigabits persecond(Gbps)  
Ethernet Serializer/Deserializer (SerDes) Transceiver. It is de-  
signedtoprovide the PhysicalMediumAttachment(PMA)portionof  
the IEEE 802.3z PHY layer.  
Pin-outs are compatible withindustrystandarddevices  
IDT77V7101/7111  
PMA CHIP  
PCS CHIP  
TXER  
TXEN  
TXD[7:0]  
GTX_CLK  
COL  
TRANSMIT  
BLOCK  
TXCG[9:0]  
TXP  
TXN  
TERMINATION  
NETWORK  
TRANSMIT  
SECTION  
TCLK  
RPT  
LEDs  
RESET  
CRS  
MDIO  
MDC  
e
c
M
a
f
CONTROL  
EWRAP  
SDT  
I
r
D
t
E
M
LINK  
CONFIG  
I
RXP  
RXN  
I
TERMINATION  
NETWORK  
M
RECEIVE  
SECTION  
G
COMDET  
ENCDET  
RXER  
RXDV  
RXD[7:0]  
RXCLK  
RECEIVE  
BLOCK  
RCLK[1:0]  
RXCG[9:0]  
7101 drw 01  
Figure 1. Typical Application Block Diagram  
APRIL 2000  
1
DSC-7101-1  
©2000IntegratedDeviceTechnology,Inc.  

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