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IDT74FCT646CTQG PDF预览

IDT74FCT646CTQG

更新时间: 2024-11-04 20:03:39
品牌 Logo 应用领域
艾迪悌 - IDT 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
8页 96K
描述
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, QSOP-24

IDT74FCT646CTQG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:QSOP-24
针数:24Reach Compliance Code:compliant
风险等级:5.43其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA
系列:FCTJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:8.6868 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):5.7 ns
认证状态:Not Qualified座面最大高度:1.7272 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9116 mm
Base Number Matches:1

IDT74FCT646CTQG 数据手册

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FAST CMOS OCTAL  
IDT74FCT646AT/CT  
TRANSCEIVER/  
REGISTER (3-STATE)  
DESCRIPTION:  
FEATURES:  
TheFCT646Tconsists ofabus transceiverwith3-stateD-typeflip-flops  
andcontrolcircuitryarrangedformultiplexedtransmissionofdatadirectly  
from the data bus or from the internal storage registers. The FCT646T  
utilizes the enable control (G) and direction (DIR) pins to control the  
transceiverfunctions.  
• A and C grades  
Low input and output leakage 1µA (max.)  
• CMOS power levels  
True TTL input and output compatibility:  
VOH = 3.3V (typ.)  
SABandSBAcontrolpinsareprovidedtoselecteitherreal-timeorstored  
data transfer.The circuitryusedforselectcontrolwilleliminate the typical  
decodingglitchthatoccurs ina multiplexerduringthe transitionbetween  
storedandreal-timedata.Alowinputlevelselectsreal-timedataandahigh  
selects storeddata.  
VOL = 0.3V (typ.)  
High Drive outputs (-15mA IOH, 64mA IOL)  
Meets or exceeds JEDEC standard 18 specifications  
• Power off disable outputs permit "live insertion"  
Available in SOIC, SSOP, and QSOP packages  
Data onthe AorBdata bus,orboth,canbe storedinthe internalDflip-  
flops by low-to-high transitions at the appropriate clock pins (CPAB or  
CPBA), regardless ofthe selectorenable controlpins.  
FUNCTIONALBLOCKDIAGRAM  
G
DIR  
CPBA  
SBA  
CPAB  
SAB  
B REG  
ONE OF EIGHT CHANNELS  
1D  
C1  
A REG  
B1  
A1  
1D  
C1  
TO SEVEN OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
FEBRUARY 2006  
1
© 2006 Integrated Device Technology, Inc.  
DSC-5505/6  

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