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IDT74FCT646D PDF预览

IDT74FCT646D

更新时间: 2024-11-15 23:11:47
品牌 Logo 应用领域
艾迪悌 - IDT 总线驱动器总线收发器触发器逻辑集成电路输入元件
页数 文件大小 规格书
8页 95K
描述
FAST CMOS OCTAL TRANSCEIVER/REGISTER

IDT74FCT646D 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:0.300 INCH, CERDIP-24针数:24
Reach Compliance Code:not_compliant风险等级:5.26
Is Samacsys:N其他特性:DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-GDIP-T24
JESD-609代码:e0长度:32.004 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:7.62 mmBase Number Matches:1

IDT74FCT646D 数据手册

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IDT54/74FCT646  
IDT54/74FCT646A  
IDT54/74FCT646C  
FAST CMOS OCTAL  
TRANSCEIVER/REGISTER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• IDT54/74FCT646 equivalent to FAST speed;  
IDT54/74FCT646A 30% faster than FAST  
IDT54/74FCT646C 40% faster than FAST  
• Independent registers for A and B buses  
• Multiplexed real-time and stored data  
• IOL = 64mA (commercial) and 48mA (military)  
• CMOS power levels (1mW typical static)  
• TTL input and output level compatible  
• CMOS output level compatible  
• Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,  
CERPACK and 28-pin LCC  
• Product available in Radiation Tolerant and Radiation  
Enhanced Versions  
The IDT54/74FCT646/A/C consists of a bus transceiver  
with 3-state D-type flip-flops and control circuitry arranged for  
multiplexed transmission of data directly from the data bus or  
from the internal storage registers.  
The IDT54/74FCT646/A/C utilizes the enable control (G)  
and direction (DIR) pins to control the transceiver functions.  
SAB and SBA control pins are provided to select either real  
time or stored data transfer. The circuitry used for select  
control will eliminate the typical decoding glitch that occurs in  
a multiplexer during the transition between stored and real-  
time data. A LOW input level selects real-time data and a  
HIGH selects stored data.  
Data on the A or B data bus or both can be stored in the  
internal D flip flops by LOW-to-HIGH transitions at the  
appropriate clock pins (CPAB or CPBA) regardless of the  
select or enable control pins.  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAM  
G
DIR  
CPBA  
SBA  
CPAB  
SAB  
1 OF 8 CHANNELS  
B REG  
1D  
C1  
A REG  
1D  
C1  
1
B1  
A
2536 drw 01  
TO 7 OTHER CHANNELS  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
FAST is a registered trademark of National Semiconductor Co.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
MAY 1992  
1992 Integrated Device Technology, Inc.  
7.18  
DSC-4626/2  
1

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