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IDT74FCT3573ASO8 PDF预览

IDT74FCT3573ASO8

更新时间: 2024-11-16 21:17:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 65K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, SOIC-20

IDT74FCT3573ASO8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-20
针数:20Reach Compliance Code:not_compliant
风险等级:5.85其他特性:BROADSIDE VERSION OF 373
系列:FCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
Prop。Delay @ Nom-Sup:5.2 ns传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

IDT74FCT3573ASO8 数据手册

 浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第2页浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第3页浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第4页浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第5页浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第6页浏览型号IDT74FCT3573ASO8的Datasheet PDF文件第7页 
3.3V CMOS OCTAL  
IDT74FCT3573/A  
TRANSPARENT  
LATCH  
DESCRIPTION:  
FEATURES:  
The FCT3573/A are octal transparent latches built using an advanced  
dual metal CMOS technology.  
• 0.5 MICRON CMOS Technology  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ±0.3V, Normal Range  
These octal latches have 3-state outputs and are intended for bus  
oriented applications. The flip-flops appear transparent to the data when  
Latch Enable (LE) is high. When LE is low, the data that meets the set-up  
time is latched. Data appears on the bus when the Output Enable (OE) is  
low. When OE is high, the bus output is in the high-impedance state.  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in QSOP, SOIC, and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
G
G
G
G
G
G
G
G
LE  
OE  
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2000  
1
© 2000 Integrated Device Technology, Inc.  
DSC-5418/4  

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