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IDT74FCT3573PY

更新时间: 2024-11-15 23:08:19
品牌 Logo 应用领域
艾迪悌 - IDT 锁存器
页数 文件大小 规格书
7页 112K
描述
3.3V CMOS OCTAL TRANSPARENT LATCHES

IDT74FCT3573PY 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:not_compliant风险等级:5.69
其他特性:BROADSIDE VERSION OF 373系列:FCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:7.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3/3.3 V
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mmBase Number Matches:1

IDT74FCT3573PY 数据手册

 浏览型号IDT74FCT3573PY的Datasheet PDF文件第2页浏览型号IDT74FCT3573PY的Datasheet PDF文件第3页浏览型号IDT74FCT3573PY的Datasheet PDF文件第4页浏览型号IDT74FCT3573PY的Datasheet PDF文件第5页浏览型号IDT74FCT3573PY的Datasheet PDF文件第6页浏览型号IDT74FCT3573PY的Datasheet PDF文件第7页 
IDT54/74FCT3573/A  
ADVANCE INFORMATION  
3.3V CMOS OCTAL  
TRANSPARENT  
LATCHES  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
TheFCT3573/Aareoctaltransparentlatchesbuiltusingan  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• 25 mil Center SSOP Packages  
• Extended commercial range of -40°C to +85°C  
• VCC = 3.3V ±0.3V, Normal Range or  
advanced dual metal CMOS technology.  
These octal latches have 3-state outputs and are intended  
for bus oriented applications. The flip-flops appear transpar-  
ent to the data when Latch Enable (LE) is HIGH. When LE is  
LOW, the data that meets the set-up time is latched. Data  
appears on the bus when the Output Enable (OE) is LOW.  
When OE is HIGH, the bus output is in the high-impedance  
state.  
VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAM  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE  
OE  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
3093 drw 01  
PIN CONFIGURATION  
FUNCTION TABLE (1)  
Inputs  
Outputs  
ON  
1
20  
19  
18  
17  
VCC  
OE  
D0  
DN  
H
LE  
H
OE  
2
3
4
O0  
O1  
O2  
O3  
O4  
L
L
H
L
D1  
D2  
L
H
P20-1  
D20-1  
X
X
H
Z
D3  
D4  
D5  
D6  
5
SO20-2 16  
NOTE:  
3093 tbl 02  
&
1. H = HIGH Voltage Level  
X = Don’t Care  
6
15  
SO20-7  
7
14  
O5  
O6  
L = LOW Voltage Level  
Z = High Impedance  
8
13  
12  
11  
9
O7  
LE  
D7  
GND  
DEFINITION OF FUNCTIONAL TERMS  
10  
Pin Names  
Description  
3093 drw 02  
DIP/SOIC/SSOP  
TOP VIEW  
DN  
Data Inputs  
LE  
OE  
ON  
ON  
Latch Enable Input (Active HIGH)  
Output Enable Input (Active LOW)  
3-State Outputs  
Complementary 3-State Outputs  
3093 tbl 03  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1995  
1995 Integrated Device Technology, Inc.  
8.13  
DSC-4648/-  
1

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