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IDT74FCT3574APGG PDF预览

IDT74FCT3574APGG

更新时间: 2024-11-16 13:08:43
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 112K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20

IDT74FCT3574APGG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83其他特性:BROADSIDE VERSION OF 374
系列:FCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):6.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

IDT74FCT3574APGG 数据手册

 浏览型号IDT74FCT3574APGG的Datasheet PDF文件第2页浏览型号IDT74FCT3574APGG的Datasheet PDF文件第3页浏览型号IDT74FCT3574APGG的Datasheet PDF文件第4页浏览型号IDT74FCT3574APGG的Datasheet PDF文件第5页浏览型号IDT74FCT3574APGG的Datasheet PDF文件第6页浏览型号IDT74FCT3574APGG的Datasheet PDF文件第7页 
IDT54/74FCT3574/A  
ADVANCE INFORMATION  
3.3V CMOS OCTAL D  
REGISTERS (3-STATE)  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
• 0.5 MICRON CMOS Technology  
The FCT3574/A are 8-bit registers built using an advanced  
dual metal CMOS technology. These registers consist of  
eight D-type flip-flops with a buffered common clock and  
buffered 3-state output control. When the output (OE) input is  
LOW, the eight outputs are enabled. When the OE input is  
HIGH, the outputs are in the high-impedance state.  
Input data meeting the set-up and hold time requirements  
of the D inputs is transferred to the O outputs on the LOW-to-  
HIGH transition of the clock input.  
• ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
• 25 mil Center SSOP Packages  
• Extended commercial range of -40°C to +85°C  
• VCC = 3.3V ±0.3V, Normal Range or  
VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Military product compliant to MIL-STD-883, Class B  
FUNCTIONAL BLOCK DIAGRAM  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
CP  
OE  
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP  
CP  
CP  
CP  
CP  
CP  
CP  
CP  
O0  
O1  
O2  
O3  
O4  
O5  
O6  
O7  
3095 drw 01  
PIN CONFIGURATION  
PIN DESCRIPTION  
Pin Names  
Description  
D flip-flop data inputs  
1
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
D
N
OE  
D0  
2
3
4
CP  
Clock Pulse for the register. Enters data on  
LOW-to-HIGH transition.  
O0  
O1  
O2  
O3  
O4  
D1  
D2  
O
O
N
N
3-state outputs, (true)  
P20-1  
D20-1  
SO20-2  
&
3-state outputs, (inverted)  
D3  
D4  
D5  
D6  
5
OE  
Active LOW 3-state Output Enable input  
6
3095 tbl 01  
7
O5  
O6  
SO20-7  
8
9
O7  
D7  
GND  
10  
CP  
DIP/SOIC/SSOP  
TOP VIEW  
3095 drw 02  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1995  
1995 Integrated Device Technology, Inc.  
8.14  
DSC-4650/-  
1

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