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IDT74FCT3573APG8 PDF预览

IDT74FCT3573APG8

更新时间: 2024-11-16 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 65K
描述
Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, TSSOP-20

IDT74FCT3573APG8 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-20
针数:20Reach Compliance Code:not_compliant
风险等级:5.85Is Samacsys:N
其他特性:BROADSIDE VERSION OF 373系列:FCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:3/3.3 VProp。Delay @ Nom-Sup:5.2 ns
传播延迟(tpd):8.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

IDT74FCT3573APG8 数据手册

 浏览型号IDT74FCT3573APG8的Datasheet PDF文件第2页浏览型号IDT74FCT3573APG8的Datasheet PDF文件第3页浏览型号IDT74FCT3573APG8的Datasheet PDF文件第4页浏览型号IDT74FCT3573APG8的Datasheet PDF文件第5页浏览型号IDT74FCT3573APG8的Datasheet PDF文件第6页浏览型号IDT74FCT3573APG8的Datasheet PDF文件第7页 
3.3V CMOS OCTAL  
IDT74FCT3573/A  
TRANSPARENT  
LATCH  
DESCRIPTION:  
FEATURES:  
The FCT3573/A are octal transparent latches built using an advanced  
dual metal CMOS technology.  
• 0.5 MICRON CMOS Technology  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
• VCC = 3.3V ±0.3V, Normal Range  
These octal latches have 3-state outputs and are intended for bus  
oriented applications. The flip-flops appear transparent to the data when  
Latch Enable (LE) is high. When LE is low, the data that meets the set-up  
time is latched. Data appears on the bus when the Output Enable (OE) is  
low. When OE is high, the bus output is in the high-impedance state.  
• VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4µW typ. static)  
• Rail-to-Rail output swing for increased noise margin  
• Available in QSOP, SOIC, and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
G
G
G
G
G
G
G
G
LE  
OE  
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
NOVEMBER 2000  
1
© 2000 Integrated Device Technology, Inc.  
DSC-5418/4  

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