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IDT74ALVCH162260PF PDF预览

IDT74ALVCH162260PF

更新时间： 2024-09-30 20:27:23
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管逻辑集成电路电视
页数 文件大小 规格书
8页 130K
描述
Multiplexer And Demux/Decoder, ALVC/VCX/A Series, 12-Func, CMOS, PDSO56, 0.40 MM PITCH, TVSOP-56

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IDT74ALVCH162260PF 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：0.40 MM PITCH, TVSOP-56
针数：56Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.89
Is Samacsys：N系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：11.3 mm逻辑集成电路类型：MULTIPLEXER AND DEMUX/DECODER
湿度敏感等级：1功能数量：12
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Logic ICs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

IDT74ALVCH162260PF 数据手册

 浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第2页浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第3页浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第4页浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第5页浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第6页浏览型号IDT74ALVCH162260PF的Datasheet PDF文件第7页 
3.3V CMOS 12-BIT TO 24-BIT  
MULTIPLEXED D-TYPE LATCH  
IDT74ALVCH162260  
WITH 3-STATE OUTPUTS  
AND BUS-HOLD  
separate data paths must be multiplexed onto, or demultiplexed from,  
a single data path. Typical applications include multiplexing and/or  
demultiplexing address and data information in microprocessor or bus-  
interface applications. This device also is useful in memory-interleav-  
FEATURES:  
–
–
–
0.5 MICRON CMOS Technology  
TypicaltSK(0) (Output Skew) < 250ps  
ESD > 2000V per MIL-STD-883, Method 3015;  
> 200V using machine model (C = 200pF, R = 0)  
0.635mm pitch SSOP, 0.50mm pitch TSSOP,  
and 0.40mm pitch TVSOP packages  
ing applications.  
–
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are  
available for address and/or data transfer. The output-enable (OE1B,  
OE2B, and OEA) inputs control the bus transceiver functions. The OE1B  
and OE2B control signals also allow bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal  
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)  
inputs are used to control data storage. When the latch-enable input is  
high, the latch is transparent. When the latch-enable input goes low, the  
data present at the inputs is latched and remains latched until the latch-  
enable input is returned high.  
–
–
–
–
–
–
Extended commercial range of – 40°C to + 85°C  
VCC = 3.3V ± 0.3V, Normal Range  
VCC = 2.7V to 3.6V, Extended Range  
VCC = 2.5V ± 0.2V  
CMOS power levels (0.4µW typ. static)  
Rail-to-Rail output swing for increased noise margin  
Drive Features for ALVCH162260:  
–
–
High Output Drivers: ± 24mA (A port)  
Balanced Output Drivers: ± 12mA (B port)  
The ALVCH162260 has series resistors in the device output structure  
of the “B” port which will significantly reduce line noise when used with  
light loads. This driver has been designed to drive ±12mA at the  
designated threshold levels. The “A” port has a ± 24mA driver.  
APPLICATIONS:  
• 3.3V High Speed Systems  
• 3.3V and lower voltage computing systems  
The ALVCH162260 has “bus-hold” which retains the inputs’ last state  
whenever the input goes to a high impedance. This prevents floating  
inputs and eliminates the need for pull-up/down resistors.  
DESCRIPTION:  
This multiplexed D-type latch is built using advanced dual metal CMOS  
technology. The ALVCH162260 is used in applications in which two  
Functional Block Diagram  
29  
OE1B  
30  
A-1B  
LEA1B  
1B1:12  
12  
LATCH  
2
1B-A  
LE1B  
12  
LATCH  
12  
12  
28  
SEL  
1
OEA  
1
M
A1:12  
U
X
12  
0
12  
12  
2B-A  
LATCH  
27  
12  
LE2B  
A-2B  
LATCH  
2B1:12  
55  
56  
12  
LEA2B  
OE2B  
EXTENDED COMMERCIAL TEMPERATURE RANGE  
MARCH1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-4628/1  
12345678

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