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IDT72V3642L15PF PDF预览

IDT72V3642L15PF

更新时间: 2024-11-30 23:01:15
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
29页 218K
描述
3.3 VOLT CMOS SyncBiFIFO 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

IDT72V3642L15PF 数据手册

 浏览型号IDT72V3642L15PF的Datasheet PDF文件第2页浏览型号IDT72V3642L15PF的Datasheet PDF文件第3页浏览型号IDT72V3642L15PF的Datasheet PDF文件第4页浏览型号IDT72V3642L15PF的Datasheet PDF文件第5页浏览型号IDT72V3642L15PF的Datasheet PDF文件第6页浏览型号IDT72V3642L15PF的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
256 x 36 x 2  
512 x 36 x 2  
IDT72V3622  
IDT72V3632  
IDT72V3642  
1,024 x 36 x 2  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving  
120-pin Thin Quad Flatpack (TQFP)  
Functionally compatible to the 5V operating IDT723622/723632/  
723642  
Industrial temperature range (–40οC to +85οC) is available  
ꢀEATURES:  
Memory storage capacity:  
IDT72V3622  
IDT72V3632  
IDT72V3642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Supports clock frequencies up to 100 MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
DESCRIPTION:  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions  
of the IDT723622/723632/723642, designed to run off a 3.3V supply for  
exceptionally low-power consumption. These devices are monolithic, high-  
speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memorieswhich  
supportclockfrequenciesupto100MHzandhavereadaccesstimesasfast  
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on  
boardeachchipbufferdatainoppositedirections.Communicationbetween  
ꢀUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
RAM  
ARRAY  
256 x 36  
512 x 36  
1,024 x 36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
10  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
1,024 x 36  
W/RB  
ENB  
MBB  
Mail 2  
Register  
4660 drw 01  
MBF2  
IDT,theIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
DECEMBER 2001  
COMMERCIAL TEMPERATURE RANGE  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4660/4  

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