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IDT72V281L15TF PDF预览

IDT72V281L15TF

更新时间: 2024-11-06 23:05:11
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路先进先出芯片时钟
页数 文件大小 规格书
26页 242K
描述
3.3 VOLT CMOS SuperSync FIFOTM

IDT72V281L15TF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:SLIM, TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.41
Is Samacsys:N最长访问时间:10 ns
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:S-PQFP-G64JESD-609代码:e0
长度:10 mm内存密度:589824 bit
内存集成电路类型:OTHER FIFO内存宽度:9
湿度敏感等级:3功能数量:1
端子数量:64字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX9可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.015 A子类别:FIFOs
最大压摆率:0.055 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

IDT72V281L15TF 数据手册

 浏览型号IDT72V281L15TF的Datasheet PDF文件第2页浏览型号IDT72V281L15TF的Datasheet PDF文件第3页浏览型号IDT72V281L15TF的Datasheet PDF文件第4页浏览型号IDT72V281L15TF的Datasheet PDF文件第5页浏览型号IDT72V281L15TF的Datasheet PDF文件第6页浏览型号IDT72V281L15TF的Datasheet PDF文件第7页 
3.3 VOLT CMOS SuperSync FIFO™  
65,536 x 9  
131,072 x 9  
IDT72V281  
IDT72V291  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin  
Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial Temperature Range (-40°C to + 85°C) is available  
ꢀEATURES:  
Choose among the following memory organizations:  
IDT72V281  
IDT72V291  
65,536 x 9  
131,072 x 9  
Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
DESCRIPTION:  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable  
settings  
Retransmit operation with fixed, low first word data  
latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of two preselected offsets  
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS  
First-In-First-Out (FIFO) memories with clocked read and write controls.  
These FIFOs offer numerous improvements over previous SuperSync  
FIFOs,includingthefollowing:  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas  
been removed. The Frequency Select pin (FS) has been removed, thus  
it is no longer necessary to select which of the two clock inputs, RCLK or  
WCLK, is runningatthe higherfrequency.  
Program partial flags by either serial or parallel means  
The period required by the retransmit operation is now fixed and short.  
Select IDT Standard timing (using EF and FF flags) or First Word Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable  
clock cycle counting delay associated with the latency period found on  
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)  
ꢀUNCTIONAL BLOCK DIAGRAM  
WEN  
D0-D8  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
65,536 x 9  
131,072 x 9  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
Q0-Q8  
4513 drw 01  
OE  
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
APRIL 2001  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE  
1
2001 Integrated Device Technology, Inc.  
DSC-4513/1  

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