Datasheet > IDT72V215

IDT72V215

更新时间： 2024-11-22 23:05:11

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	216K
描述
3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18

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IDT72V215 数据手册

3.3 VOLT CMOS SyncFIFO^TM

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

IDT72V205, IDT72V215,

IDT72V225, IDT72V235,

IDT72V245

FEATURES:

DESCRIPTION:

• 256 x 18-bit organization array (IDT72V205)

• 512 x 18-bit organization array (IDT72V215)

• 1,024 x 18-bit organization array (IDT72V225)

• 2,048 x 18-bit organization array (IDT72V235)

• 4,096 x 18-bit organization array (IDT72V245)

• 10 ns read/write cycle time

TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-

patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,

designed to run off a 3.3V supply for exceptionally low power consumption.

These devices are very high-speed, low-power First-In, First-Out (FIFO)

memorieswithclockedreadandwritecontrols. TheseFIFOsareapplicable

forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local

AreaNetworks(LANs),andinterprocessorcommunication.

• 5V input tolerant

• IDT Standard or First Word Fall Through timing

• Single or double register-buffered Empty and Full flags

• Easily expandable in depth and width

• Asynchronous or coincident Read and Write Clocks

• Asynchronous or synchronous programmable Almost-Empty

and Almost-Full flags with default settings

• Half-Full flag capability

• Output enable puts output data bus in high-impedanc state

• High-performance submicron CMOS technology

• Available in a 64-lead thin quad flatpack (TQFP/STQFP)

• Industrial temperature range (–40°C to +85°C) is available

TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled

byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread

intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput

portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).

TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.

AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol

oftheoutput.

ThesynchronousFIFOshavetwofixedflags,EmptyFlag/OutputReady

(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,

Almost-Empty(PAE)andAlmost-Full(PAF). Theoffsetloadingoftheprogram-

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0-D17

WEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

FLAG

WRITE CONTROL

LOGIC

EF/OR

PAE

LOGIC

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

HF/(WXO)

READ POINTER

WRITE POINTER

WXI

READ CONTROL

LOGIC

EXPANSION LOGIC

(HF)/WXO

RXI

RXO

OUTPUT REGISTER

RESET LOGIC

4294 drw 01

REN

RCLK

Q0-Q17

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

FEBRUARY 2002

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4294/3

12 3 4 5 6 7...25

中文翻译

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与IDT72V215相关器件

型号	品牌	获取价格	描述	数据表
IDT72V215L10PF	IDT	获取价格	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
IDT72V215L10PF8	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72V215L10PF9	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
IDT72V215L10PFI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
IDT72V215L10TF	IDT	获取价格	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
IDT72V215L10TF8	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64
IDT72V215L10TF9	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64
IDT72V215L10TFG8	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64, SLIM, PLASTIC, TQFP-64
IDT72V215L10TFI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
IDT72V215L10TP	IDT	获取价格	FIFO, 512X18, 6.5ns, Synchronous, CMOS, PQFP64

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