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IDT72815LB10PF PDF预览

IDT72815LB10PF

更新时间: 2024-09-15 22:57:23
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
26页 330K
描述
CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18, and DUAL 4,096 x 18

IDT72815LB10PF 数据手册

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IDT72805LB  
IDT72815LB  
IDT72825LB  
IDT72835LB  
IDT72845LB  
CMOS DUAL SyncFIFO™  
DUAL 256 x 18, DUAL 512 x 18,  
DUAL 1,024 x 18, DUAL 2,048 x 18  
and DUAL 4,096 x 18  
Single or double register-buffered Empty and Full Flags  
FEATURES:  
Easily expandable in depth and width  
The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs  
The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs  
The IDT72825LBis equivalenttotwoIDT72225LB1,024 x 18FIFOs  
The IDT72835LBis equivalenttotwoIDT72235LB2,048 x 18FIFOs  
The IDT72845LBis equivalenttotwoIDT72245LB4,096 x 18FIFOs  
Offers optimal combination of large capacity (8K), high speed,  
design flexibility, and small footprint  
Asynchronous or coincident Read and Write clocks  
Asynchronous or synchronous programmable Almost-Empty  
and Almost-Full flags with default settings  
Half-Full flag capability  
Output Enable puts output data bus in high-impedance state  
High-performance submicron CMOS technology  
Available in the 128-pin Thin Quad Flatpack (TQFP). Also  
available for the IDT72805LB/72815LB/72825LB, in the 121-lead,  
16 x 16 mm plastic Ball Grid Array (PBGA)  
Ideal for the following applications:  
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-
-
-
-
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Network switching  
Two level prioritization of parallel data  
Bidirectional data transfer  
Bus-matching between 18-bit and 36-bit data paths  
Width expansion to 36-bit per package  
Depth expansion to 8,192 words per package  
Industrial temperature range (–40°C to +85°C) is available  
DESCRIPTION:  
TheIDT72805LB/72815LB/72825LB/72835LB/72845LBaredual18-bit-wide  
synchronous(clocked)First-in,First-out(FIFO)memories.OnedualIDT72805LB/  
72815LB/72825LB/72835LB/72845LB device is functionally equivalent to two  
10ns read/write cycle time, 6.5ns access time  
IDT Standard or First Word Fall Through timing  
FUNCTIONAL BLOCK DIAGRAM  
HFA/(WXOA)  
PAEA  
FFA/IRA  
EFA/  
ORA  
WCLKA  
WCLKB  
DA0-DA17  
WENA  
LDA  
WENB  
DB0-DB17  
LDB  
PAFA  
INPUT  
OFFSET  
INPUT  
OFFSET  
REGISTER  
REGISTER  
REGISTER  
REGISTER  
FFB/IRB  
FLAG  
PAFB  
WRITE  
FLAG  
LOGIC  
WRITE  
EFB/ORB  
PAEB  
HFB/(WXOB)  
CONTROL  
LOGIC  
RAM  
LOGIC  
CONTROL  
LOGIC  
ARRAY  
RAM  
256 x 18  
512 x 18  
1,024 x 18  
2,048 x 18  
4,096 x 18  
ARRAY  
256 x 18  
512 x 18  
1,024 x 18  
2,048 x 18  
4,096 x 18  
READ  
POINTER  
WRITE  
READ  
POINTER  
WRITE  
POINTER  
POINTER  
READ  
CONTROL  
LOGIC  
FLA  
WXIA  
(HFA)/WXOA  
RXIA  
READ  
CONTROL  
LOGIC  
EXPANSION  
LOGIC  
EXPANSION  
LOGIC  
OUTPUT  
REGISTER  
OUTPUT  
RXOA  
REGISTER  
RESET  
LOGIC  
RSA  
RESET  
LOGIC  
RSB  
RXOB  
RXIB  
(HFB)/WXOB  
WXIB  
FLB  
RCLKB  
RCLKA  
OEB  
QA0-QA17  
RENB  
RENA  
OEA  
QB0-QB17  
3139 drw 01  
IDTandtheIDTlogoareregisteredtrademarks.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2003  
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3139/4  

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