IDT72421L25PFG

更新时间： 2024-11-05 13:08:43

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
14页	155K
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数据手册

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IDT72421L25PFG 数据手册

CMOSSyncFIFO^™

64 x 9, 256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT72421,IDT72201

IDT72211,IDT72221

IDT72231,IDT72241

IDT72251

FEATURES:

DESCRIPTION:

•

64 x 9-bit organization (IDT72421)

256 x 9-bit organization (IDT72201)

512 x 9-bit organization (IDT72211)

1,024 x 9-bit organization (IDT72221)

2,048 x 9-bit organization (IDT72231)

4,096 x 9-bit organization (IDT72241)

8,192 x 9-bit organization (IDT72251)

10 ns read/write cycle time

Read and Write Clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full Flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can be set

to any depth

Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

Output enable puts output data bus in high-impedance state

Advanced submicron CMOS technology

Available in the 32-pin plastic leaded chip carrier (PLCC) and

32-pin Thin Quad Flat Pack (TQFP)

The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clockedreadandwrite controls. These devices have a 64, 256, 512, 1,024,

2,048,4,096,and8,192x9-bitmemoryarray,respectively. TheseFIFOsare

applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea

networksandinterprocessorcommunication.

TheseFIFOshave9-bitinputandoutputports.Theinputportiscontrolled

bya free-runningclock(WCLK), andtwowrite enable pins (WEN1, WEN2).

DataiswrittenintotheSynchronousFIFOoneveryrisingclockedgewhenthe

writeenablepinsareasserted.Theoutputportiscontrolledbyanotherclock

pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can

betiedtotheWriteClockforsingleclockoperationorthetwoclocks canrun

asynchronous ofoneanotherfordual-clockoperation.Anoutputenablepin

(OE)is providedonthe readportforthree-state controlofthe output.

The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag

offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting

•

For through-hole product please see the IDT72420/72200/72210/ the load pin (LD).

72220/72230/72240 data sheet

These FIFOs are fabricated using IDT’s high-speed submicron CMOS

technology.

Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

D0 - D8

WCLK

WEN1

WEN2

OFFSET REGISTER

INPUT REGISTER

FLAG

LOGIC

WRITE CONTROL

LOGIC

PAE

PAF

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1,024 x 9,

2,048 x 9, 4,096 x 9,

8,192 x 9

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

2655 drw01

Q0 - Q8

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

SEPTEMBER 2002

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-2655/2



12 3 4 5 6 7...14

中文翻译

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与IDT72421L25PFG相关器件

型号	品牌	获取价格	描述	数据表
IDT72421L25PFGI	IDT	获取价格	FIFO, 64X9, 15ns, Synchronous, CMOS, PQFP32, GREEN, TQFP-32
IDT72421L25PFI	IDT	获取价格	CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72421L25PFI9	IDT	获取价格	FIFO, 64X9, 15ns, Synchronous, CMOS, PQFP32, TQFP-32
IDT72421L25PFISCDS-W	IDT	获取价格	FIFO, 64X9, 15ns, Synchronous, CMOS, PQFP32
IDT72421L25PFSCDS-W	ETC	获取价格	x9 Synchronous FIFO
IDT72421L35J	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72421L35J8	IDT	获取价格	FIFO, 64X9, Synchronous, CMOS, PQCC32, 0.050 INCH PITCH, PLASTIC, LCC-32
IDT72421L35JB	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72421L35JSCDS-W	ETC	获取价格	x9 Synchronous FIFO
IDT72421L35L	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

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