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IDT72420L50TCB PDF预览

IDT72420L50TCB

更新时间: 2024-11-10 22:57:23
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
16页 167K
描述
CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

IDT72420L50TCB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, THIN, SIDE BRAZED, DIP-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.85最长访问时间:25 ns
最大时钟频率 (fCLK):20 MHz周期时间:50 ns
JESD-30 代码:R-CDIP-T28JESD-609代码:e0
长度:35.56 mm内存密度:512 bit
内存集成电路类型:OTHER FIFO内存宽度:8
功能数量:1端子数量:28
字数:64 words字数代码:64
工作模式:SYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:64X8
输出特性:3-STATE可输出:YES
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP28,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B
座面最大高度:5.08 mm最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.04 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.62 mm

IDT72420L50TCB 数据手册

 浏览型号IDT72420L50TCB的Datasheet PDF文件第2页浏览型号IDT72420L50TCB的Datasheet PDF文件第3页浏览型号IDT72420L50TCB的Datasheet PDF文件第4页浏览型号IDT72420L50TCB的Datasheet PDF文件第5页浏览型号IDT72420L50TCB的Datasheet PDF文件第6页浏览型号IDT72420L50TCB的Datasheet PDF文件第7页 
IDT72420  
IDT72200  
IDT72210  
IDT72220  
IDT72230  
IDT72240  
CMOS SyncFIFO  
64 x 8, 256 x 8, 512 x 8,  
1024 x 8, 2048 x 8 and 4096 x 8  
Integrated Device Technology, Inc.  
FEATURES:  
• 64 x 8-bit organization (IDT72420)  
• 256 x 8-bit organization (IDT72200)  
• 512 x 8-bit organization (IDT72210)  
DESCRIPTION:  
The IDT72420/72200/72210/72220/72230/72240  
SyncFIFO are very high-speed, low-power First-In, First-  
Out (FIFO) memories with clocked read and write controls.  
The IDT72420/72200/72210/72220/72230/72240 have a 64,  
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-  
tively. These FIFOs are applicable for a wide variety of data  
buffering needs, such as graphics, Local Area Networks  
(LANs), and interprocessor communication.  
These FIFOs have 8-bit input and output ports. The input  
port is controlled by a free-running clock (WCLK), and a write  
enable pin (WEN). Data is written into the Synchronous FIFO  
on every clock when WEN is asserted. The output port is  
controlled by another clock pin (RCLK) and a read enable pin  
(REN). The read clock can be tied to the write clock for single  
clock operation or the two clocks can run asynchronous of one  
another for dual clock operation. An output enable pin (OE) is  
provided on the read port for three-state control of the output.  
TheseSynchronousFIFOshavetwoend-pointflags, Empty  
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and  
Almost-Full (AF), are provided for improved system control.  
Thepartial(AE)flagsaresettoEmpty+7andFull-7forAE and  
AF respectively.  
• 1024 x 8-bit organization (IDT72220)  
• 2048 x 8-bit organization (IDT72230)  
• 4096 x 8-bit organization (IDT72240)  
• 12 ns read/write cycle time (IDT72420/72200/72210)  
• 15 ns read/write cycle time (IDT72220/72230/72240)  
• Read and write clocks can be asynchronous or  
coincidental  
• Dual-Ported zero fall-through time architecture  
• Empty and Full flags signal FIFO status  
• Almost-empty and almost-full flags set to Empty+7 and  
Full-7, respectively  
• Output enable puts output data bus in high-impedance  
state  
• Produced with advanced submicron CMOS technology  
• Available in 28-pin 300 mil plastic DIP and 300 mil  
ceramic DIP  
• For surface mount product please see the IDT72421/  
72201/72211/72221/72231/72241 data sheet  
• Military product compliant to MIL-STD-883, Class B  
• Industrial temperature range (-40OC to +85OC) is  
available, tested to military electrical specifications  
The IDT72420/72200/72210/72220/72230/72240 are fabri-  
cated using IDT’s high-speed submicron CMOS technology.  
Military grade product is manufactured in compliance with the  
latest revision of MIL-STD-883, Class B.  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D7  
WCLK  
WEN  
INPUT REGISTER  
EF  
AE  
AF  
FF  
FLAG  
WRITE CONTROL  
LOGIC  
LOGIC  
RAM ARRAY  
64 x 8  
256 x 8  
512 x 8  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
RS  
REN  
OE  
2680 drw 01  
Q0 - Q7  
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
NOVEMBER 1996  
1996 Integrated Device Technology, Inc.  
DSC-2680/6  
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.  
5.12  
1

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